MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 74

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor, Inc.
is converted to a digital word in the – (sigma–delta) ADC (analog–to–digital converter). After filter-
ing, an adaptively generated replica of the transmitted signal, calculated by the echo canceller, is sub-
tracted from the combined signal leaving only the far–end signal. In addition, phase distortion present
in the far–end signal is corrected by the DFE. The resulting four–level signal is decoded by the slicer
to produce a 160 kbps data stream. Timing information is also recovered from the far–end signal. The
Superframe Deframer descrambles and disassembles the received superframes and passes the
received 2B+D data through a three IDL frame deep FIFO to the IDL interface, where it is available at
the D out pin of the time division multiplexed data interface.
The MC145572 permits the designer to select one of three options for control of the device and access
to its register set. When operating in MCU mode, the MC145572 can be configured for either SCP
or PCP mode of operation. In SCP mode, control and status of the device is handled via the SCP,
a standard four–wire serial microcontroller interface. In PCP mode, the MC145572 is configured to
provide an eight–bit wide data port with a chip select and read/write pin. In either case, the internal
register set of the MC145572 gives an external microcontroller access to the 4 kbps Maintenance
channel provided across the U–interface.
When the MC145572 is configured for GCI mode, the C/I channel of the GCI interface is used for
control and status messages. The GCI Monitor channel is used to send and receive Maintenance
channel messages. The Monitor channel also permits the internal registers of the MC145572 to be
read from or written to, if it is desired to bypass the normal operation of the GCI interface.
The eoc portion of the M channel can be handled automatically with the internal Automatic eoc Pro-
cessor. In addition, activation and deactivation of the MC145572 is handled by an Automatic Activation
Controller.
The MC145572 requires a single 20.48000 MHz pullable crystal connected between the XTAL in and
XTAL out pins. No other external components are required for the crystal oscillator. Internal crystal
pulling circuitry adjusts the crystal frequency in both LT and NT modes of operation.
Detailed descriptions of the various interfaces and user accessible sections are provided in this
chapter.
5.2
MC145472/MC14LC5472 COMPATIBILITY
After either a hardware or software reset, the MC145572 maintains basic pin function and register
compatibility with the MC14LC5472 U–interface transceiver when configured for MCU mode and using
the SCP interface. There are differences between MC14LC5472 and MC145572 in exact signal re-
quirements and outputs for these pins.
Most software written for MC14LC5472 will operate MC145572 without requiring any modifications.
The MC145572 has an extended register set which provides access to the on–chip timeslot assigner,
I/O pin configuration bits, D channel, and internal parameters of the device. The extended registers
are accessed by setting bits in Register BR10 that were reserved bits for MC14LC5472. The new
registers then overlay the original registers and are referred to in this document as Overlay registers
OR0 through OR9, OR12, and OR13. Register BR10 is common to both register sets, permitting soft-
ware to switch between the basic register set and the overlay register set, as required. Tables 4–1,
4–2, and 4–3 detail the register set of MC145527. See Chapter 4, Register Description, for details
on the register set.
Tables 5–1 and 5–2 contain the MC145572 pin function charts. The MC145572 requires a line interface
transformer having a turns ratio of 1:1.25 where the 1.25 is on the tip and ring side of the transformer.
The MC14LC5472 used a line interface transformer having a 1:2 turns ratio.
When operated in MCU mode with the SCP, MC145572 has clock outputs enabled on 15.36 CLKOUT
and BUFXTAL pins after a hardware or software reset. On MC14LC5472, these clocks were disabled
after a hardware or software reset. Due to this change, the function of bits BR15A(b2, b1) have changed
in MC145572. In MC14LC5472, these two bits enabled 15.36 CLKOUT and BUFXTAL outputs, respec-
tively; when set to 1. In MC145572, these bits are reserved and writing a 1 to either of these bits
to enable a clock, leaves the clock(s) enabled. To disable one or both of these clocks, software must
set either bit b2 or bit b1 in Overlay register OR9.
For More Information On This Product,
5–2
MC145572
MOTOROLA
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