MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 59

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
M4 Dual Consecutive Modes (b5, b4 = 0,0 or 0,1)
The M4 Dual Consecutive modes perform a simple algorithm on the received M4 bits, and only interrupt
the external microcontroller when an M4 bit has changed state and has remained in the new state
for two consecutive superframes. The M4 bit values read from BR1 in this mode are only the most
recent values that have been the same for two consecutive superframes. Referring to Table 4–12,
suppose, for example, that for several superframes the M4 bits have been all 0s, as shown in the
column labeled “Received M4 Byte”. If the external microcontroller read BR1, it would read all 0s as
shown in the column labeled “BR1 Contents”. Now, notice in the subsequent superframes 2 and 3
that the received M4 bits that do not hold their state for at least two consecutive superframes, do
not cause an interrupt and do not show up in BR1.
At start–up, there is no history of what has been received in the M4 bits. Therefore, the technique
for the initial setting for BR1 is as follows: a hardware or software reset sets BR1 to all 0s. However,
at the user’s discretion, while either Linkup (NR1(b3)) or Superframe Sync (NR1(b1)) is 0, the user
may write to BR1 and set the initial value. In this way, the external microcontroller may assume a
current state for the M4 bits, and then wait for an IRQ1 to inform it of a change in state. Also, any
time that Superframe Sync is lost and then regained, the initial programmed value is reloaded into
BR1.
The default M4 Dual Consecutive mode (b5, b4 = 0,0) has the additional feature of performing auto-
matic detection of the act and dea bits. Verified act (BR3(b2)) and Verified dea ((BR3(b1)) are dual
consecutive checked values of M40 and M41. Verified act is valid for both NT and LT modes. Verified
dea operates in the NT mode only. Whenever there is a 0 to 1 transition on Superframe Sync
(NR1(b1)), Verified act and Verified dea are reset. If M40 is received as 1 for two consecutive super-
frames, Verified act is set to 1. Similarly, if M40 is received as 0 for two consecutive superframes,
Verified act is set to 0. When this mode is selected, the logical OR of Verified act and the Customer
Enable bit in NR2(b0) permits customer data transparency without any action taken by the external
microcontroller. In NT mode, if M41 is received for two consecutive superframes as 0, Verified dea
is set to 1. Similarly, if M41 is received as 1 for two consecutive superframes, Verified dea will return
to 0. When this mode is selected, the logical OR of Verified dea and the Deactivate Request bit in
NR2(b2) allows the U–interface transceiver to respond to the far–end transceiver’s intention to deacti-
vate without requiring any interaction by the external microcontroller. Note that the state of Verified
act and Verified dea may be monitored by the external microcontroller through BR3(b2:b1).
OR7
0
0
0
0
1
Superframe
BR9 M4 Control 1:0
b5
Freescale Semiconductor, Inc.
X
0
0
1
1
1
2
3
For More Information On This Product,
Table 4–12. M4 Dual Consecutive Modes Example
Table 4–11. M4 Control Modes
Go to: www.freescale.com
b4
0
1
0
1
X
Received M4 Byte
0000 0000
1000 0001
0001 0001
M4 Dual Consecutive mode. In addition, the Verified act (BR3(b2)) and
Verified dea (BR3(b1)) operations are enabled in this mode only.
M4 Dual Consecutive mode.
Delta mode.
Every mode.
M4 channel bits M40 (act), M41 (dea), and M46 (uoa, sai) are
trinal–checked. Remaining bits operate per BR9(b5,b4) settings. Verified act
and Verified dea available on trinal–checked act, dea bits when b5:b4 = 0,0.
MC145572
BR1 Contents
M4 Function Description
0000 0000
0000 0000
0000 0001
IRQ1 is set
Action
—
—
4–23