MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 28

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

3–6
3.3.3
Time Division Multiplex Data Interface Pins
This section describes the Time Division Multiplex (TDM) data interface pins.
MCU/GCI: MCU/GCI Select Input
A logic 1 applied to this pin selects the MCU mode. This requires an external MCU to access
the internal control/status register of the MC145572. 2B+D data only is transferred over the
time division multiplex bus. In MCU mode, four data formats are available on the IDL2 interface.
These are short frame, long frame, GCI 2B+D, and timeslot assigner. A logic 0 applied to
this pin selects the GCI time division bus mode.
In GCI mode, 2B+D data and control/status information is interfaced to the MC145572 by
a single four signal time division multiplexed bus. The SCP interface is not used and those
pins are redefined.
In full GCI mode, both MCU/GCI and PAR/SER must be connected to V SS .
PAR/SER: Parallel/Serial Select Input
This pin allows parallel versus serial control port selection when the MC145572 is operating
in MCU mode. PAR/SER = 1 selects parallel port operation. PAR/SER = 0 selects serial con-
trol port operation. This pin must be connected to V SS when MCU/GCI is connected to V SS
(i.e., in full GCI mode).
M/S: Master/Slave Select Input
The TDM interface can be configured as a Master or a Slave with the M/S pin. A logic 1 input
at this pin selects the Master mode and a logic 0 selects the Slave mode. The polarity of this
pin can be inverted using BR7(b1).
When the MC145572 is configured for master timing and MCU mode, the FSR/FSC, FSX,
and DCL pins are outputs and their signals are generated internally. As a Master, the U–
interface transceiver provides a 2.048 MHz, 2.56 MHz, or 512 kHz DCL output as selected
in BR7(b2) and OR7(b4).
When the MC145572 is configured for slave timing and MCU mode, the FSR/FSC, FSX, and
DCL pins are inputs and their signals are provided externally. As a Slave, the TDM interface
block is designed to accept any clock rate from 256 kHz to 4.096 MHz, inclusive.
In GCI Master mode, FSC, D out , and DCL pins are outputs and D in is an input. Either the
512 kHz or 2.048 MHz clock is available on DCL. FSX is not used.
In GCI Slave mode, D out is an output and FSC, DCL, and D in are inputs. FSX is not used.
DCL can accept clock rates up to 8.192 MHz.
FSR/FSC
FSR: MCU Mode Frame Synchronization Receive
FSR is the 8 kHz frame sync for the receive data of the TDM interface. In short frame
and timeslot assigner mode, the signal at this pin is high for one cycle of the DCL signal
Freescale Semiconductor, Inc.
For More Information On This Product,
NOTES: PCP — Parallel Control Port, external MCU uses
GCI
MCU/PCP
MCU/SCP
Table 3–6. Operation Mode as Indicated by
Go to: www.freescale.com
Mode
SCP — Serial Control Port, external MCU uses
MC145572
8–bit data port to access registers.
four signal serial ports to access registers.
Mode Input Pins
MCU/GCI
0
1
1
PAR/SER
0
1
0
MOTOROLA