MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 29

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
FSX: MCU Mode Frame Synchronization Transmit
FSX is the 8 kHz frame sync for the transmit data of the MCU interface. This pin is not used
in the GCI mode. The formatting of FSX is mode dependent.
This pin is an input when the TDM interface is in the Slave mode and an output in Master
mode, as established by the M/S pin.
When the MC145572 is in NT mode and M/S = 1, this output is phase locked to the signal
received at the U–interface. As an LT in the Master mode, this output is derived directly from
the 20.48 MHz master clock. The frequency of the periodic FSR signal is 8 kHz. As a Slave,
the FSX signal must occur at an average rate of 8 kHz (125 s interval) with a maximum phase
deviation from a jitter free sync of
In Master mode, FSR and FSX output the same waveform. In Slave mode, both FSR and
FSX inputs must be driven by external circuitry. FSR and FSX inputs can be tied together
in the Slave mode and a common sync can be used to drive both inputs.
DCL: Data Clock Input/Output
This pin is an input when the TDM interface is in the Slave mode and an output in the Master
mode, as established by the M/S pin.
As a timing master in the MCU–NT mode, this pin provides a 2.048 MHz, 512 kHz, or a
2.56 MHz MCU clock output. This choice is programmed in BR7(b2) and OR7(b4). Also see
Section 5.4.
When configured as a slave in MCU mode, this pin accepts any clock frequency from 256 kHz
to 4.096 MHz, inclusive.
In GCI mode, this pin provides clock outputs 2.048 MHz or 512 kHz, as selected by CLKSEL.
In GCI Slave mode, this pin accepts clock frequencies of 512 kHz to 8.192 MHz, inclusive.
In NT master timing of operation, recovered timing is conveyed over DCL by adjusting the
width of the clock. The adjustment is made by the internal digital PLL and occurs during two
consecutive 8 kHz frames, once per U–interface basic frame. The adjustment consists of
and is rising edge aligned with the rising edge of the DCL signal. This pin is an input when
the TDM interface is in Slave mode and an output in the Master mode as established
by the M/S pin. See Figures 5–17 through 5–20.
When the MC145572 is in NT mode and M/S = 1, this output is phase locked to the signal
received at the U–interface. As an LT in the Master mode, this output is derived directly
from the 20.48 MHz master clock. The frequency of the periodic FSR signal is 8 kHz. As
a Slave, the FSR signal must occur at an average rate of 8 kHz (125 s interval) with
a maximum phase deviation from a jitter–free sync of
In Master mode, FSR and FSX output the same waveform. In Slave mode, both FSR and
FSX inputs must be driven by external circuitry. FSR and FSX inputs can be tied together
in Slave mode and a common sync can be used to drive both inputs.
FSC: GCI Mode Frame Synchronization Receive
In full GCI mode and in GCI 2B+D mode, this pin serves as the FSC pin, and the signal
is high for two cycles of the DCL signal and the rising edge is aligned with the rising edge
of the DCL signal. This pin is an input when the TDM interface is in Slave mode and an
output in Master mode as established by the M/S pin. FSC indicates a superframe
boundary by going high for one DCL clock. This happens once every 12 ms.
When the MC145572 is in NT mode and M/S = 1, this output is phase locked to the signal
received at the U–interface.
As an LT in the Master mode, this output is derived directly from the 20.48 MHz master
clock. The frequency of the periodic FSR signal is 8 kHz.
As a Slave, the FSC signal must occur at an average rate of 8 kHz (125 s interval) with
a maximum phase deviation from a jitter free sync of
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MC145572
48 s.
48 s.
48 s.
3–7