MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 39

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
BR10
OR12
OR13
OR0
OR1
OR2
OR3
OR4
OR5
OR6
OR7
OR8
OR9
4.2.1
4.2
D/R Mode 1
Loopback
Reserved
Reserved
TSA B1
Internal
Enable
Analog
b7
REGISTER MAP
The register map consists of six 4–bit nibble registers (NR0 – NR5), one 12–bit nibble register (R6),
seventeen byte registers (BR0 – BR15A), and twelve overlay registers (OR0 – OR9, OR11, and OR12).
Register Index
The following guide lists the registers alphabetically by functional groups and indicates which register
number; NR0 – NR5, R6, or BR0 – BR15A, and bit or bits, (b7:b0); to refer to for detailed information.
Activation
Control — BR11(b7:b1)
Control Steer — BR12(b7)
Customer Enable — NR2(b0)
Deactivation Request — NR2(b2)
Error Indication — NR1(b2)
Error Power Indicator — BR12, BR13
Force Linkup — BR12(b0)
Hold Activation State — BR12(b3)
In Progress — NR1(b0)
Jump Select — BR12(b2)
Linkup — NR1(b3)
Load Activation State — BR12(b5)
Request — NR2(b3)
State — BR11(b7:b1)
Line Connect
D/R Mode 0
Feedback
Reserved
Switches
TSA B2
INIT GROUP REGISTER OVERLAY REGISTERS OR0 – OR9, OR11, AND OR12
Enable
Open
b6
Table 4–3. Overlay Register Map (OR0 – OR13)
Freescale Semiconductor, Inc.
For More Information On This Product,
SFAX Output
D Channel
Loopback
Reserved
Enable
Enable
Enable
Analog
TSA D
TSEN
b5
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Dump/Restore Access Select Overlay
D out B1 Channel Timeslot Bits (7:0)
D out B2 Channel Timeslot Bits (7:0)
D Channel Access Select Overlay
D out D Channel Timeslot Bits (7:0)
D in B1 Channel Timeslot Bits (7:0)
D in B2 Channel Timeslot Bits (7:0)
Dump Register Write Access (7:0)
Dump Register Read Access (7:0)
D in D Channel Timeslot Bits (7:0)
D Channel Transmit Bits (7:0)
D Channel Receive Bits (7:0)
IDL2 Rate 2
GCI Select
FREQREF
Reserved
M4– OR0
CLKOUT
MC145572
Output
Enable
2048
b4
TSEN Enable
Long Frame
4096 Hirate
GCI Mode
Reserved
Diagnostics
Enable
B1, B2
Mode
IDL2
b3
Accumulate DFE Output — BR13(b3)
Accumulate EC Output — BR13(b6)
Clear All Coefficients — BR13(b0)
Enable Clocks — BR14(b0)
Enable DFE Updates — BR13(b2)
Enable EC Updates — BR13(b5)
Enable Eye Data and Baud Clock — BR15A(b0)
Enable MEC Updates — BR13(b7)
Enable TxSFS — BR15A(b3)
Enable 15.36 MHz — BR15A(b2)
Enable 20.48 MHz — BR15A(b1)
Error Power Indicator — BR12, BR13
Fast DFE/ARC Beta — BR13(b1)
1 Tones — BR14(b3)
Select Dump
2048 Disable
crc Corrupt
Reserved
Reserved
Access
Mode
b2
GCI Slot (2:0)
1536 Disable
SFAX SFAR
Select DCH
febe/nebe
Reserved
Rollover
Access
Enable
b1
4096 Disable
Port Enable
Select INIT
D Channel
Reserved
M4 Trinal
Group
Mode
b0
4–3