MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 60

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

4–24
4.4.11
M4 Delta Mode (b5, b4 = 1,0)
The Delta mode compares the M4 data from the previous superframe against the current received
superframe M4 data. If there is a difference in at least one bit, BR1 is updated and an IRQ1 interrupt
is issued. Note that in this mode, BR1 always contains a copy of the latest received M4 byte from
the previous superframe.
M4 Every Mode (b5, b4 = 1,1)
The Every mode stores each received superframe of M4 data in BR1 and issues an interrupt at the
end of every received superframe.
Note that regardless of the mode of operation, BR1 will not be altered while Superframe Sync
(NR1(b1)) is 0.
M4 Trinal–Check Mode
The M4 act, dea, sai, and uoa bits can be configured for trinal–check operation by setting OR7(b0)
to a 1. See Section 4.5.8 for more detail.
M5/M6 Control 1:0
These bits control the M5/M6 handling capability of the U–interface transceiver. The default mode
setting is b3, b2 = 0,0, which selects the Dual Consecutive mode. These controls are identical in opera-
tion to the M4 mode control functions, except that they apply to M50, M51, and M60. Refer to the
M4 Control mode paragraphs above for a description of the M5/M6 Control modes. The M5/M6 inter-
rupt, IRQ0 (NR3(b0)), occurs in the middle of the superframe when basic frame 4 has been completely
received.
febe/nebe Control
This bit controls how the transmitted febe is computed. If this bit is 0, the transmitted febe is set
active if either the Computed nebe (BR3(b3)) is active or the febe input (BR2(b4)) is set active. If
this control bit is set to 1, the transmitted febe is set to whatever is set in the febe input (BR2(b4)).
BR10: Overlay Select Register
This register is used to enable access to the overlay register set of the MC145572. To maintain future
compatibility, the reserved bits must be written as 0s.
BR10
Reserved
b7
Freescale Semiconductor, Inc.
For More Information On This Product,
Regarding febe and nebe, “active” means they are set to 0.
M5/M6 Control 1:0
b3
Reserved
0
1
1
b6
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Table 4–13. M5/M6 Control Modes
Don’t Care
Reserved
b2
0
1
MC145572
b5
M5/M6 Dual Consecutive mode.
Delta mode.
Every mode.
Reserved
NOTE
b4
M5/M6 Function Description
Reserved
b3
Access
Select
Dump
b2
rw
Access
Select
DCH
b1
rw
MOTOROLA
Overlay
Select
b0
rw