MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 43

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
Error Indication
This bit is set to 1 when a timer expires. Time–out sources are:
1. 15–second Activation Timer (BR11(b0)).
2. 480–ms loss of frame/signal.
3. Failure to get NT1 response to the TL signal (10 ms following the cessation of TL). (TL is 3 ms in
Error Indication is always automatically reset prior to the next IRQ3. This is the result of either setting
the Activate Request bit in NR2(b3) or receiving a wakeup tone. Error Indication is not cleared by
reading NR1.
See D Channel Interrupt below for operation of this bit when D channel access has been enabled
by setting BR10(b1).
Superframe Sync
This bit is a 1 when the received superframe is being reliably detected. It transitions from 0 to 1 coin-
cident with Linkup being set. Subsequently, if the superframe is lost, Superframe Sync returns to 0,
and if Superframe Sync remains 0 for 480 ms, the U–interface transceiver will deactivate. While Super-
frame Sync is 0, the received maintenance bits are unknown. IRQ2, IRQ1, and IRQ0 are not generated
while Superframe Sync is 0. The 2B + D data is blocked (forced to all 1s) when Superframe Sync is
0.
See D Channel Interrupt below for operation of this bit when D channel access has been enabled
by setting BR10(b1).
Transparent/Activation in Progress
This bit has a dual purpose. When the transceiver is deactivated, this bit is 0. Whenever an activation
begins, this bit is internally set to a 1 and an IRQ3 is generated. When the activation process is
completed, Linkup is set to 1 indicating success, and this bit remains set to 1, indicating that the
receiver and Superframe Deframer are ready to pass data transparently from the U–interface to the
IDL2 interface. If the activation process fails, this bit is cleared and Error Indication is set to 1. When-
ever Linkup is 1, this bit may be cleared, indicating that the receiver has detected a high error on
the U–interface. Under this condition, the receiver blocks received data (forcing the 2B + D data to
all 1s) until the error returns to normal.
See D Channel Interrupt below for operation of this bit when D channel access has been enabled
by setting BR10(b1).
D Channel Interrupt
When access to the D channel register OR12 has been enabled by setting BR10(b1), the operation
of the NR1 status bits is modified. A D channel available status is indicated by NR1(b3:b0) all being
set to 1s. Software must first do a check for NR1 = $F, then perform a check for status of the individual
bits. The D channel interrupt is cleared by reading OR12.
duration.)
The received data is not transmitted on the IDL2 interface until Linkup is 1, Superframe Sync
is 1, Transparent/Activation in Progress is 1, and either Customer Enable (see NR2(b0)) or
Verified act (see BR3(b2)) is 1.
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MC145572
NOTE
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