MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 118

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

7–2
7.2
7.3
EMBEDDED OPERATIONS SUBCHANNEL
The eoc subchannel can operate in one of three modes. The eoc register, R6, can be updated and
an interrupt generated on every received eoc frame, and on a successful trinal–check of a new eoc
frame. This applies to the NT and LT modes of operation. In NT mode, the MC145572 also provides
an Automatic eoc Processor for automatic decoding and response to the ANSI T1.601–1992 eoc mes-
sages. The R6 update occurs only when Superframe Sync, NR2(b1), has been detected and set to
a 1. When the microcontroller writes to eoc register R6, the new eoc word is loaded into the Superframe
Framer on the next eoc frame boundary, assuming the automatic eoc mode is not enabled. These
modes are selected by eoc Control 1 and eoc Control 0, BR9(b7:b6).
In Trinal–Check mode, R6 is updated when three consecutively received eoc frames are the same.
When the automatic eoc mode with trinal–check has been selected and the U–interface transceiver
is operating as an NT, the decoded eoc is acted on when a valid trinal–check has occurred and R6
is updated.
R6 can be configured to update on every eoc frame by setting eoc Control 1 and eoc Control 0,
BR9(b7:b6), each to a 1. The update occurs every 6 ms, even if no change has been detected between
eoc frames. This mode must be used for proprietary and non–ISDN basic rate applications.
R6 is updated in all modes of operation. This permits an external microcontroller to monitor eoc mes-
sages when the Automatic eoc Processor is enabled in NT mode. R6 is updated at the mid–point
or at the end of a superframe.
Regardless of the mode of operation, an update of R6 generates an interrupt whenever Enable IRQ2,
NR4(b2), is set to a 1.
M4 SUBCHANNEL AND DATA TRANSPARENCY
The M4 subchannel operates in one of four modes set in BR9(b5:b4). The received M4 data from the
Superframe Deframer is available in BR1. The transmitted M4 subchannel data is written to Byte reg-
ister BR0. See BR9 in Section 4.4.10 and Verified act and Verified dea, BR3(b2:b1), in Sec-
tion 4.4.4 for more details on the M4 channel register operations. When set to a 1, the M4 Trinal Mode
bit, OR7(b0), configures the M4 uoa, sai, dea, and act bits to be updated after a trinal–check. See
descriptions for BR0, BR9, and OR7 for more details.
M4 Control mode 0,0 is the dual consecutive mode of operation with automatic verification of the M4
act bit in LT and NT modes and automatic verification of the M4 dea bit in NT mode. In this mode,
once Superframe Sync, NR2(b1), is set to a 1, BR1 and Verified act, BR3(b2), are updated when the
Superframe Deframer detects that an M4 channel bit has changed state and has remained in that
state for two consecutive superframes. The M4 maintenance subchannel bits act, dea, sai, and
uoa can be configured for trinal–checking by setting OR7(b0) to a 1.
When OR7(b0) is set to a 1, the received M4 bit positions in BR1 corresponding to act, dea, sai,
and uoa are updated on a trinal–check regardless of the programmed M4 Control bits in BR9(b5, b4).
The remaining bits in BR1 are updated according to the programmed M4 Control bits in BR9(b5, b4).
Note that the Verified act/dea mode BR9(b5, b4) = 0,0 operates on trinal–checked M4 act and dea
bits when OR7(b0) is a 1. See Table 4–7 and Sections 4.4.10 and 4.5.8.
In either the LT or NT modes of operation, customer data transparency is achieved by the logical OR
of Verified act, BR3(b3), and Customer Enable, NR2(b0). This means when the received M4 act bit
is a 1 and the M4 channel is configured in the Verified act/dea mode, data transparency is automati-
cally enabled. If the Verified act/dea mode is not enabled, Customer Enable, NR2(b0), must be set
to a 1 to permit transmission of 2B+D data onto the U–interface.
When Customer Enable, NR2(b0), is set to a 1, data transparency occurs on the next IDL frame
boundary, not the next superframe boundary. The recommended procedure is for firmware in NT1 to
assert the act bit, BR0(b7), to a 1 after it has determined that NT1 is ready for layer two transmission.
This should be immediately followed by setting Customer Enable, NR2(b0), to a 1. Section 6.4.6.6 of
Read text in Section 4.4.10 concerning Trinal–Check mode very carefully.
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MC145572
CAUTION
MOTOROLA