MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 87

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
5.4
IDL2 TIME DIVISION BUS INTERFACE
The IDL2 interface consists of six pins: M/S, FSX, FSR, DCL, D in , and D out . With the M/S pin, the
IDL2 interface can be configured as a timing master (FSR, FSX, and DCL are outputs) or a timing
slave (FSR, FSX, and DCL are inputs). The master or slave configuration is independent of NT or
LT mode selection. The IDL2 interface receives 2B+D data on the D in pin and buffers it through a
FIFO to the U–interface Superframe Framer. Simultaneously, this block accepts 2B+D data from the
U–interface Superframe Deframer, buffers it through a FIFO, and transmits it out the D out pin. Refer
to Figure 5–1 for a block diagram of the MC145572.
After a hardware or software reset, the MC145572 IDL2 interface is configured for short frame opera-
tion. Short frame format is compatible with the IDL interface timing used on the MC145472 U–interface
transceiver. Table 5–3 details how to configure the MC145572 for the different IDL2 interface data
formats. In both short frame and long frame formats, two frame sync signals are available: FSX and
FSR. In GCI 2B+D data format, a single frame sync, FSC, is available.
The 2B+D data is transferred over IDL2 interface at an 8 kHz rate. Each IDL2 2B+D frame contains
eight bits of B1 channel data, eight bits of B2 channel data, and two bits of D channel data. The IDL2
interface supports five different frame formats and a timeslot assigner. The frame formats are long
frame and short frame synchronization, each with either 8– or 10–bit 2B+D data formats. The fifth
frame format is the IDL2 GCI electrical frame format. In this format, only the 2B+D data bits of the
GCI interface are accessible by MC145572. Either SCP or PCP must be used for access to the internal
register set of MC145572 when IDL2 operation is enabled.
As a master, the IDL2 interface of MC145572 can be configured to output 512 kHz, 2.048 MHz, or
2.56 MHz clock rates at the DCL pin. Table 5–4 is a guide to IDL2 clock rate selection. These data
rates apply to all IDL2 frame formats, including the GCI 2B+D data format. Please note that when
configured for GCI electrical operation, the data rate is one–half the DCL clock rate.
As a slave, the IDL2 interface of MC145572 accepts clock rates from 256 kHz to 4.096 MHz at the
DCL pin.
A separate D channel port is available when configured for MCU SCP operation.
NOTE: The timeslot assigner is enabled when one or more of OR6(b7 or b6 or b5) are set to a 1. Enabling the timeslot assigner
IDL2 Short Frame Format
10–Bit Frame Size
(MC145472 Compatible)
IDL2 Short Frame Format
8–Bit Frame Size
(MC145472 Compatible)
IDL2 Long Frame Format
10–Bit Frame Size
IDL2 Long Frame Format
8–Bit Frame Size
GCI 2B+D Frame Format
IDL2 Data Format
overrides all other IDL2 frame formats.
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5–3. IDL2 Interface Data Format Selection
Go to: www.freescale.com
OR6
(b3)
0
0
0
0
1
MC145572
OR7
(b3)
0
0
1
1
0
BR7
(b0)
0
1
0
1
0
FSX, FSR
FSX, FSR
FSX, FSR
FSX, FSR
Available
Frame
Syncs
FSC
D Channel
Available
Port
Yes
Yes
Yes
No
No
Default after hardware or
software reset
Comments
5–15