MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 107

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
5.6.5
Below is the procedure to perform the MC145572 Superframe Framer–to–Deframer loopback on the
MC145572.
To turn off the Superframe Framer–to–Deframer loopback.
External Analog Loopback
An external analog loopback is shown in Figure 5–37. As the shaded portion of the block diagram
shows, this loopback mode takes B and D channel data in at the D in pin, and transmits the data out
the Tx Driver pins. The 2B1Q signal passes through the external line interface circuitry and back into
the receiver input pins. The signal is then recovered and sent out the D out pin. It is recommended
that Tip and Ring be physically disconnected from the U–interface twisted wire pair. This is perhaps
the easiest way to assure that the transmitted signal is not properly terminated, resulting in very little
trans–hybrid loss. Do not use a 135–ohm termination resistor.
OR7 bits 6 and 7 can be used to modify operation of the analog loopback. In order to use them, they
must be set prior to setting OR9 (b5). These bits must be cleared after the analog loopback is turned
off. These bits are cleared after any reset. See OR7 description for more details.
Since the entire 2B1Q superframe is being looped back, loopback data includes the 2B+D channels
and all of the M channels. For instance, data written by an external microcontroller to the eoc, M4,
and M5/M6 registers (R6, BR0, and BR2), is looped back and can be read from the eoc, M4, and
M5/M6 registers (R6, BR1, and BR3).
For both NT and LT applications, ensure that a 10 k
Procedure to enable analog loopback when operating NT/LT pin is connected to V DD (NT mode).
Make sure that there is a 10 k pulldown resistor on the SFAX pin.
Set BR8(b0) = 1 to put the selected MC145572 into LT mode. (For devices with the NT/LT pin
connected to V DD .)
Set BR8(b0) = 0 to ensure the selected MC145572 is in LT mode. (For devices with the NT/LT
pin connected to V SS .)
Wait 5 seconds for the MC145572 on–chip PLL to stabilize. Write the following data to the
MC145572 registers.
Configure the IDL bus or timeslot assigner for the bus format required to send/receive data with
the MC145572.
The MC145572 is ready for the loopback test when NR1 reads as $0B.
BR8(b0) = 1
Delay 5 seconds to allow PLL to stabilize.
BR10 = $01
OR8 = $22
OR9 = $20
BR10 = $00
BR14 = $10
BR8 = $B7
BR12 = $89
BR13 = $0C
NR2 = $01
BR14 = $00
BR8 = $00
BR12 = $00
BR13 = $00
Freescale Semiconductor, Inc.
For More Information On This Product,
Put into LT mode.
Enable Overlay Register set.
Enable SFAX pin as output (only required for applications that
do not have the 10 k
Enable Analog Loopback.
Disable Overlay Register set.
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MC145572
Pulldown Resistor).
pulldown resistor is connected to SFAX pin.
5–35