MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 115

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
6.11.1
6.10
6.11
6.8
6.9
limit on how long NR1 may read as $A when data transparency is lost. There is a 480–ms time limit
on NR1 reading as $8. ANSI T1.601 only indicates that U–interface transceivers must deactivate when
Superframe Synchronization or receive signal is lost for more than 480 ms. If the error condition goes
away, NR1 returns to $B and an interrupt is generated, if enabled.
Loss of Superframe Synchronization may be due to a high internally detected error rate on recovered
data or the temporary loss of received signal.
NT DEACTIVATION PROCEDURES AND WARM START
ANSI T1.601 specifies that NT can not initiate deactivation. The MC145572 deactivates to a warm
start condition when Deactivation Request (NR2(b2)) is set to a 1 prior to LT deactivating the U–inter-
face. This should be done in response to the M4 channel dea bit being received as 0 by NT when the
loop is active. If Deactivation Request (NR2(b2)) is not set to a 1 before LT deactivates the U–inter-
face, MC145572 deactivates to a cold start condition and gives an error indication interrupt. Deacti-
vation Request is automatically set if the M4 maintenance bits are operated with automatic verification
of activation and deactivation. So when LT deactivates the line, NT deactivates to a warm start condi-
tion. See BR9(b5:b4) and OR7(b0) for more information.
LT DEACTIVATION PROCEDURES
ANSI T1.601 specifies that only LT can deactivate the U–interface. This is done in the MC145572
by setting Deactivation Request (NR2(b2)) to a 1.
Prior to deactivating, LT should notify NT of the pending deactivation by clearing the M4 channel dea
bit towards NT for at least three superframes. Then, deactivate LT by setting Deactivation Request
(NR2(b2)) to a 1.
The MC145572, when configured as an LT, has a mode in which the M4 channel can be updated and
sent for exactly three superframes before deactivation occurs. This is done in the following manner.
Set Superframe Update Disable (NR2(b1)) to a 1 to disable maintenance channel updates. Reset the
M4 channel dea bit (BR0(b6)) to a 0 to indicate that the LT initiated deactivation. Reset Superframe
Update Disable (NR2(b1)) to a 0 and simultaneously set Deactivation Request (NR2(b2)) to a 1 to
re–enable maintenance channel updates and initiate deactivation. The LT U–interface transceiver
then updates the maintenance channel Superframe Framer bits and sends exactly three superframes
with the M4 channel dea bit reset to a 0. The U–interface transceiver then deactivates per ANSI
T1.601–1992.
INITIAL STATE OF B1 AND B2 CHANNELS
The MC145572 comes out of hardware or software reset with customer data disabled. This corre-
sponds to Customer Enable (NR2(b0)) reset to 0. When the M4 channel Verified act/dea mode is not
used, it is required that Customer Enable (NR1(b0)) be set to a 1, to enable data transparency when
NR1 becomes $B after initial activation. The B1, B2, and D channels transmitted on the IDL interface
are automatically enabled after the MC145572 activates. Data on the B1 channel from the U–inter-
face corresponds to data in the B1 channel timeslot on the IDL interface. Data on the B2 channel from
the U–interface corresponds to data on the B2 channel timeslot on the IDL interface. The B1 and B2
channel timeslots on the IDL interface can be swapped by setting Swap B1/B2 (NR5(b0)) to a 1.
ADDITIONAL NOTES
Maintenance Channel Bits
The received eoc, M4, M5, and M6 channel bits are available in registers R6, BR1, and BR3 once
linkup has been attained. The Customer Enable bit (NR2(b0)) affects only the two B channels and
the D channel. See BR0 – BR3 and BR9 descriptions for a full description of the maintenance channel
bits and their control.
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MC145572
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