MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 47

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
Basic Frame #
Basic Frame #
act = start up bit, set = 0 during start up
aib = alarm indication bit (set = 0 to indicate interruption)
sco = 0 start on command only
act = start up bit, set = 1 during start up
crc = cyclic redundancy check: covers 2B + D + M4
cso = cold start only ( set = 1 for cold start only)
Bit Positions
Bit Positions
crc = cyclic redundancy check: covers 2B + D + M4
dea = turn off bit (set = 0 to indicate turn off)
eoc = embedded operations channel
dm = data/message indicator (0 = data, 1 = message)
Positions
Positions
1 = reserved bit for future standard (set = 1)
a = address bit
QUAT
QUAT
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Table 4–5. Register Bit Locations Within the Superframe LT
Table 4–6. Register Bit Locations Within the Superframe NT
Sync Word
Sync Word
Freescale Semiconductor, Inc.
Framing
Framing
1 – 18
1 – 18
1 – 9
1 – 9
ISW
ISW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
For More Information On This Product,
12 x 2B+D
12 x 2B+D
12 x 2B+D
12 x 2B+D
12 x 2B+D
12 x 2B+D
12 x 2B+D
12 x 2B+D
12 x 2B+D
12 x 2B+D
12 x 2B+D
12 x 2B+D
12 x 2B+D
12 x 2B+D
12 x 2B+D
12 x 2B+D
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10 – 117
19 – 234
10 – 117
19 – 234
2B+D
2B+D
2B+D
2B+D
MC145572
118s
118s
235
eoc
eoc
eoc
eoc
eoc
eoc
eoc
eoc
235
eoc
eoc
eoc
eoc
eoc
eoc
eoc
eoc
M1
dm
dm
M1
dm
dm
a1
a1
a1
a1
i3
i6
i3
i6
i3
i6
i3
i6
ps1, ps2 = power status bits, (set = 0 to indicate power problems)
febe = far–end block error
febe = far–end block error
ntm = NT in test mode bit (set = 0 to indicate test mode)
uoa = U–only–activation
sai = S–activation indicator bit (optional, set = 1 for S/T
nib = network indicator bit
eoc = embedded operations channel
118m
dm = data/message indicator (0 = data, 1 = message)
118m
236
eoc
eoc
eoc
eoc
eoc
eoc
eoc
eoc
M2
236
eoc
eoc
eoc
eoc
eoc
eoc
eoc
eoc
a2
a2
M2
i1
i4
i7
i1
i4
i7
a2
a2
a = address bit
i1
i4
i7
i1
i4
i7
activity)
Overhead Bits (M1 – M6)
Overhead Bits (M1 – M6)
119s
119s
237
eoc
eoc
eoc
eoc
eoc
eoc
eoc
eoc
M3
237
eoc
eoc
eoc
eoc
eoc
eoc
eoc
eoc
a3
a3
M3
i2
i5
i8
i2
i5
i8
a3
a3
i2
i5
i8
i2
i5
i8
119m
119m
act
dea
sco
238
uoa
act
ntm
cso
sai
nib
M4
238
ps1
ps2
aib
M4
1
1
1
1
crc11
crc11
crc1
crc3
crc5
crc7
crc9
120s
crc1
crc3
crc5
crc7
crc9
120s
239
239
M5
M5
1
1
1
1
NT
LT
crc10
crc12
crc10
crc12
120m
febe
crc2
crc4
crc6
crc8
120m
febe
crc2
crc4
crc6
crc8
240
240
M6
M6
1
1
4–11