MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 165

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
10.7.1
10.7
IDL2 TIMING
IDL2 Master Short Frame Sync Timing, 8-
and TSAC Formats
NOTES:
Ref. No.
1. FSR or FSX occurs on average every 125 s.
2. The DCL frequency may be 512 kHz, 2.048 MHz, or 2.56 MHz.
3. The duty cycle of DCL is between 45% and 55% when operated in Master Timing mode. This duty cycle is guaranteed for
4. The pulse width during the low phase of the clock varies between 45% and 55% of the nominal frequency. Timing adjust-
5. In IDL 8– and 10–bit formats, TSEN can be valid during the B1, B2, and D channel timeslots.
10
11
12
13
1
2
3
4
5
6
7
8
9
all DCL clocks, except the clock that is used for making timing adjustments, in order to maintain synchronization with the
received signal when operating in NT mode. In NT Master mode, the MC145572 conveys timing adjustments over the DCL
clock of the device. This is done by adding or subtracting a single 20.48 MHz clock period of 48 ns to the high phase of DCL
clock on two successive IDL frames, once per U–interface basic frame. The total adjustment is 96 ns distributed over the
two IDL frames. When DCL is configured for 2.048 MHz or 2.56 MHz, the adjustment occurs during clock pulse number
249 after FSX/FSR. The count starts at clock pulse 0 for the DCL clock immediately following FSX/FSR. When DCL is con-
figured for 512 kHz, the adjustment occurs during DCL pulse number 59. It is important to remember this when using the
timeslot assigner, since it is possible to program it to transfer 2B or D data during the clock period where the timing adjust-
ment is being made and this may effect setup and hold times for other components in a system.
ments are not made during the low phase of DCL.
FSR or FSX Period
Delay From the Rising Edge of DCL to the Rising Edge of
FSX or FSR
Delay From the Rising Edge of DCL to the Falling Edge of
FSX or FSR
DCL Clock Period
DCL Pulse Width High, Nominal
DCL Clock 249 Pulse Width High
DCL Clock 59 Pulse Width High
DCL Pulse Width Low
Delay From Rising Edge of DCL to Low–Z and Valid Data
on D out
Delay From Rising Edge of DCL to Data Valid on D out
Delay From Rising Edge of DCL to High–Z on D out
Data Valid on D in Before Falling Edge of DCL (D in Setup
Time)
Data Valid on D in After Falling Edge of DCL (D in Hold Time)
Delay From Rising Edge of DCL to TSEN Low
Delay From Falling Edge of DCL to TSEN High
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Parameter
MC145572
2.048 MHz
2.048 MHz
2.56 MHz
2.56 MHz
512 kHz
512 kHz
Min
125
391
878
210
170
160
120
825
and
45
25
25
—
—
—
—
—
—
5
10-Bit
Typ
125
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1953
1074
1120
Max
265
215
315
265
—
30
30
55
30
30
30
—
—
30
30
% of DCL
Period
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
Note
10–3
1
2
3
4
5