MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 117

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
MCU MODE MAINTENANCE CHANNEL OPERATION
7.1
INTRODUCTION
When configured for MCU mode operation, the MC145572 provides a very flexible interface to the
4 kbps maintenance channel (M channel), defined in ANSI T1.601–1992. The maintenance channel
consists of 48 bits sent by both the LT and NT configured U–interface transceivers during the course
of a superframe. These 48 bits are divided into 6 subchannels, designated M1 through M6, each con-
sisting of 8 bits per superframe. The eoc consists of M1, M2, and M3. The overhead bits, such as crc,
febe, act, and dea, are contained in subchannels M4, M5, and M6.
An external microcontroller can read from or write to the maintenance channel via the SCP or PCP
interfaces. Interrupts to an external microcontroller can be enabled when an eoc, M4, M5, or M6 chan-
nel register is updated. Maintenance channel registers can be configured to update when a new value
is detected between successive superframes, when a bit changes, or when two or three successive
superframes of a new value are detected. The M4 channel act bit, BR1(b7), can also be configured
to automatically enable or disable customer data when in NT or LT mode of operation. The M4 chan-
nel dea bit, BR1(b6), can also be configured to automatically issue a deactivation request in NT mode
of operation. The maintenance channel registers are updated only when Superframe Sync, NR1(b1),
is set to a 1.
Sections 7.5 and 7.6 provide information of interest to designers of LULT/LUNT (Line Unit Like–LT/
Line Unit Like–NT1) type line cards for use in digital loop carrier systems using end–to–end perfor-
mance monitoring.
See the BR9 description in Section 4.4.10 for more details on maintenance channel register opera-
tions. Figure 7–1 shows the relationship between the received superframe and when the interrupt line
is asserted when the appropriate interrupts have been enabled.
The text in this chapter is based on an ANSI T1.601 compliant application. Due to the flexibility of
the MC145572 register interface, it can easily be used in proprietary applications.
FRAME NO.
NOTE: Since the eoc register, R6, is updated after basic frames 4 and 8, IRQ2 can occur at either location, or both,
depending on the setting of BR9(B7:b6).
1
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 7–1. Maintenance Channel Interrupt Timing
2
Go to: www.freescale.com
3
MC145572
- IRQ0, IRQ2
- M5/M6 CHANNELS UPDATED
- eoc UPDATE
- UPDATE
1 SUPERFRAME, 12 ms
4
febe
STATUS BIT
5
6
7
- IRQ1, IRQ2
- M4 CHANNEL UPDATE
- eoc UPDATE
- UPDATE
8
nebe
STATUS BIT
7
7–1