PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 146

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J53 FAMILY
TABLE 10-3:
DS39964B-page 146
RA0/AN0/C1INA/
ULPWU/PMA6/
RP0
RA1/AN1/C2INA/
V
RA2/AN2/C2INB/
C1IND/C3INB/
V
RA3/AN3/C1INB/
V
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
Note 1:
BG
REF
REF
/PMA7/RP1
-/CV
+
Pin
REF
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and
PIC18LF47J53).
PORTA I/O SUMMARY
Function
ULPWU
PMA6
PMA7
C1INA
C2INA
C2INB
C1IND
C3INB
CV
C1INB
V
V
RA0
AN0
RP0
RA1
AN1
RP1
RA2
AN2
RA3
AN3
V
REF
REF
BG
REF
(1)
(1)
+
-
Setting
TRIS
1
0
1
1
1
x
1
0
1
0
1
1
x
1
0
1
0
0
1
1
1
0
1
1
1
x
0
1
1
1
1
I/O
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ST/TTL/
ST/TTL Parallel Master Port (io_addr_in[7]).
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
TTL
DIG
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
TTL
DIG
I/O
ST
ST
Preliminary
PORTA<0> data input; disabled when analog input is enabled.
LATA<0> data output; not affected by analog input.
A/D Input Channel 0 and Comparator C1- input. Default
input configuration on POR; does not affect digital output.
Comparator 1 Input A.
Ultra low-power wake-up input.
Parallel Master Port digital I/O.
Remappable Peripheral Pin 0 input.
Remappable Peripheral Pin 0 output.
PORTA<1> data input; disabled when analog input is enabled.
LATA<1> data output; not affected by analog input.
A/D Input Channel 1 and Comparator C2- input. Default
input configuration on POR; does not affect digital output.
Comparator 1 Input A.
Band Gap Voltage Reference output. (Enabled by setting
the VBGOE bit (WDTCON<4>.)
Parallel Master Port address.
Remappable Peripheral Pin 1 input.
Remappable Peripheral Pin 1 output
LATA<2> data output; not affected by analog input. Disabled
when CV
PORTA<2> data input. Disabled when analog functions are
enabled; disabled when CV
A/D Input Channel 2 and Comparator C2+ input. Default
input configuration on POR; not affected by analog output.
Comparator 2 Input B.
CTMU pulse generator charger for the C2INB comparator
input.
Comparator 1 Input D.
Comparator 3 Input B.
A/D and comparator voltage reference low input.
Comparator voltage reference output. Enabling this feature
disables digital I/O.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input is enabled.
A/D Input Channel 3 and Comparator C1+ input. Default
input configuration on POR.
Comparator 1 Input B
A/D and comparator voltage reference high input.
REF
output enabled.
Description
REF
 2010 Microchip Technology Inc.
output is enabled.