PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 385

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

23.2.3
The USB Status register reports the transaction status
within the SIE. When the SIE issues a USB transfer
complete interrupt, USTAT should be read to determine
the status of the transfer. USTAT contains the transfer
endpoint number, direction and Ping-Pong Buffer
Pointer value (if used).
The USTAT register is actually a read window into a
4-byte status FIFO, maintained by the SIE. It allows the
microcontroller to process one transfer while the SIE
processes additional endpoints (Figure 23-3). When
the SIE completes using a buffer for reading or writing
data, it updates the USTAT register. If another USB
transfer is performed before a transaction complete
interrupt is serviced, the SIE will store the status of the
next transfer into the status FIFO.
REGISTER 23-3:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-3
bit 2
bit 1
bit 0
Note 1:
Note:
U-0
—
USB STATUS REGISTER (USTAT)
This bit is only valid for endpoints with available Even and Odd BD registers.
The data in the USB Status register is valid
only when the TRNIF interrupt flag is
asserted.
Unimplemented: Read as ‘0’
ENDP<3:0>: Encoded Number of Last Endpoint Activity bits
(represents the number of the BDT updated by the last USB transfer)
1111 = Endpoint 15
1110 = Endpoint 14
.
.
.
0001 = Endpoint 1
0000 = Endpoint 0
DIR: Last BD Direction Indicator bit
1 = The last transaction was an IN token
0 = The last transaction was an OUT or SETUP token
PPBI: Ping-Pong BD Pointer Indicator bit
1 = The last transaction was to the Odd BD bank
0 = The last transaction was to the Even BD bank
Unimplemented: Read as ‘0’
ENDP3
R-x
USTAT: USB STATUS REGISTER (ACCESS F64h)
W = Writable bit
‘1’ = Bit is set
ENDP2
R-x
ENDP1
R-x
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F47J53 FAMILY
ENDP0
Clearing the transfer complete flag bit, TRNIF, causes
the SIE to advance the FIFO. If the next data in the
FIFO holding register is valid, the SIE will reassert the
interrupt within 5 T
data is present, TRNIF will remain clear; USTAT data
will no longer be reliable.
FIGURE 23-3:
R-x
Note:
4-Byte FIFO
for USTAT
Data Bus
automatically issue a NAK back to the host.
If an endpoint request is received while the
USTAT
DIR
R-x
CY
USTAT from SIE
of clearing TRNIF. If no additional
FIFO
USTAT FIFO
x = Bit is unknown
is
PPBI
R-x
full,
(1)
DS39964B-page 385
Clearing TRNIF
Advances FIFO
the
SIE
U-0
—
bit 0
will