PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 574

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J53 FAMILY
Extended Instruction Set
External Clock Input ............................................................ 38
F
Fail-Safe Clock Monitor............................................. 441, 455
Fast Register Stack............................................................. 85
Firmware Instructions........................................................ 459
Flash Program Memory..................................................... 109
FSCM. See Fail-Safe Clock Monitor.
G
GOTO................................................................................ 480
H
Hardware Multiplier ........................................................... 119
High/Low-Voltage Detect .................................................. 419
I
I/O Ports ............................................................................ 141
DS39964B-page 574
ADDFSR ................................................................... 502
ADDULNK ................................................................. 502
CALLW...................................................................... 503
MOVSF ..................................................................... 503
MOVSS ..................................................................... 504
PUSHL ...................................................................... 504
SUBFSR ................................................................... 505
SUBULNK ................................................................. 505
Interrupts in Power-Managed Modes ........................ 457
POR or Wake-up From Sleep ................................... 457
WDT During Oscillator Failure .................................. 456
Associated Registers ................................................ 118
Control Registers ...................................................... 110
Erase Sequence ....................................................... 114
Erasing ...................................................................... 114
Operation During Code-Protect ................................ 118
Reading..................................................................... 113
Table Pointer
Table Pointer Boundaries ......................................... 112
Table Reads and Table Writes ................................. 109
Write Sequence ........................................................ 115
Writing ....................................................................... 115
8 x 8 Multiplication Algorithms .................................. 119
Operation .................................................................. 119
Performance Comparison (table) .............................. 119
Applications............................................................... 423
Associated Registers ................................................ 424
Characteristics .......................................................... 532
Current Consumption ................................................ 421
Effects of a Reset...................................................... 424
Operation .................................................................. 420
Setup......................................................................... 421
Start-up Time ............................................................ 421
Typical Application .................................................... 423
Open-Drain Outputs .................................................. 142
Pin Capabilities ......................................................... 141
Associated Registers, Reception ...................... 366
Associated Registers, Transmission................. 365
Reception.......................................................... 366
Transmission..................................................... 365
EECON1 and EECON2 .................................... 110
TABLAT (Table Latch) Register........................ 112
TBLPTR (Table Pointer) Register ..................... 112
Boundaries Based on Operation....................... 112
Unexpected Termination................................... 118
Write Verify ....................................................... 118
During Sleep ..................................................... 424
Preliminary
I
I
INCF ................................................................................. 480
INCFSZ............................................................................. 481
In-Circuit Debugger........................................................... 458
In-Circuit Serial Programming (ICSP)....................... 441, 458
Indexed Literal Offset Addressing
Indexed Literal Offset Mode.............................................. 506
Indirect Addressing ........................................................... 104
INFSNZ............................................................................. 481
Initialization Conditions for All Registers....................... ??–80
Instruction Cycle ................................................................. 86
Instruction Set................................................................... 459
2
2
C Mode........................................................................... 310
C Mode (MSSP)
TTL Input Buffer Option ............................................ 142
Acknowledge Sequence Timing ............................... 338
Associated Registers ................................................ 344
Baud Rate Generator ............................................... 331
Bus Collision
Clock Arbitration ....................................................... 333
Clock Stretching........................................................ 325
Clock Synchronization and CKP bit .......................... 326
Effects of a Reset ..................................................... 339
General Call Address Support .................................. 329
I
Master Mode............................................................. 329
Multi-Master Communication, Bus Collision
Multi-Master Mode .................................................... 339
Operation .................................................................. 315
Read/Write Bit Information (R/W Bit) ................ 315, 318
Registers .................................................................. 310
Serial Clock (SCLx Pin) ............................................ 318
Slave Mode............................................................... 315
Sleep Operation........................................................ 339
Stop Condition Timing .............................................. 338
and Standard PIC18 Instructions.............................. 506
Clocking Scheme........................................................ 86
Flow/Pipelining............................................................ 86
ADDLW..................................................................... 465
ADDWF..................................................................... 465
ADDWF (Indexed Literal Offset Mode) ..................... 507
ADDWFC .................................................................. 466
ANDLW..................................................................... 466
ANDWF..................................................................... 467
BC............................................................................. 467
BCF .......................................................................... 468
BN............................................................................. 468
BNC .......................................................................... 469
2
C Clock Rate w/BRG.............................................. 332
During a Repeated Start Condition................... 342
During a Stop Condition ................................... 343
10-Bit Slave Receive Mode (SEN = 1) ............. 325
10-Bit Slave Transmit Mode ............................. 325
7-Bit Slave Receive Mode (SEN = 1) ............... 325
7-Bit Slave Transmit Mode ............................... 325
Operation.......................................................... 331
Reception ......................................................... 335
Repeated Start Condition Timing ..................... 334
Start Condition Timing ...................................... 333
Transmission .................................................... 335
and Arbitration .................................................. 339
Addressing........................................................ 315
Addressing Masking Modes
Reception ......................................................... 318
Transmission .................................................... 318
5-Bit .......................................................... 316
7-Bit .......................................................... 317
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