PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 49

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.2
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
4.2.1
The PRI_RUN mode is the normal, full-power execu-
tion mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 28.4 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set (see
Section 3.5.1 “Oscillator Control Register”).
4.2.2
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of low-power consumption while still using a
high-accuracy clock source.
SEC_RUN mode is entered by setting the SCS<1:0>
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 4-1), the primary
oscillator
(OSCCON2<6>) is set and the OSTS bit is cleared.
FIGURE 4-1:
FIGURE 4-2:
 2010 Microchip Technology Inc.
Peripheral
Program
Run Modes
Counter
T1OSI
OSC1
Note 1: T
Clock
Clock
CPU Clock
is
PRI_RUN MODE
SEC_RUN MODE
CPU
PLL Clock
Peripheral
Program
Counter
Output
T1OSI
OSC1
Clock
shut
Q1
SCS<1:0> Bits Changed
OST
Q2
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
down,
PC
= 1024 T
Q3
Q4
the
Q1
OSC
Q1
T
; T
OST
1
SOSCRUN
PLL
(1)
PC
Q2
= 2 ms (approx). These intervals are not shown to scale.
2
Clock Transition
T
3
PLL
OSTS Bit Set
Q3
Preliminary
(1)
bit
Q4
PC + 2
n-1
PIC18F47J53 FAMILY
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
Figure 4-2). When the clock switch is complete, the
SOSCRUN bit is cleared, the OSTS bit is set and the
primary clock would be providing the clock. The IDLEN
and SCS bits are not affected by the wake-up; the
Timer1 oscillator continues to run.
Q1
1
n
Note:
Transition
2
Clock
n-1 n
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS<1:0> bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, device clocks will be delayed until
the oscillator has started. In such situa-
tions, initial oscillator operation is far from
stable and unpredictable operation may
result.
Q2
PC + 2
Q3
Q2
Q4
Q3 Q4
Q1
Q1
PC + 4
Q2
Q2
PC + 4
DS39964B-page 49
Q3
Q3