PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 449

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

REGISTER 28-8:
REGISTER 28-9:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-4
bit 3
bit 2
bit 1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4-0
DEV2
U-1
—
R
Unimplemented: Program the corresponding Flash Configuration bit to ‘1’
LS48MHZ: Low-Speed USB Clock Selection
1 = 48-MHz system clock is expected; divide-by-8 generates low-speed USB clock
0 = 24-MHz system clock is expected; divide-by-4 generates low-speed USB clock
Unimplemented: Read as ‘0’
WPEND: Write-Protect Disable bit
1 = Flash pages, WPFP<6:0> to (Configuration Words page), are write/erase protected
0 = Flash pages 0 to WPFP<6:0> are write/erase-protected
WPDIS: Write-Protect Disable bit
1 = WPFP<5:0>, WPEND and WPCFG bits are ignored; all Flash memory may be erased or written
0 = WPFP<5:0>, WPEND and WPCFG bits enabled; erase/write-protect is active for the selected
DEV<2:0>: Device ID bits
These bits are used with DEV<10:3> bits in Device ID Register 2 to identify the part number. See
Register 28-10.
REV<4:0>: Revision ID bits
These bits are used to indicate the device revision.
DEV1
region(s)
U-1
—
R
CONFIG4H: CONFIGURATION REGISTER 4 HIGH (BYTE ADDRESS 300007h)
DEVID1: DEVICE ID REGISTER 1 FOR PIC18F47J53 FAMILY DEVICES
(BYTE ADDRESS 3FFFFEh)
WO = Write-Once bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
DEV0
U-1
—
R
REV4
U-1
Preliminary
—
R
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
LS48MHZ
PIC18F47J53 FAMILY
R/WO-1
REV3
R
REV2
U-0
—
R
x = Bit is unknown
x = Bit is unknown
WPEND
R/WO-1
REV1
R
DS39964B-page 449
R/WO-1
WPDIS
REV0
R
bit 0
bit 0