PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 157

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 10-9:
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
 2010 Microchip Technology Inc.
PORTD
LATD
TRISD
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
Note 1:
RD6/PMD6/
RP23
RD7/PMD7/
RP24
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I
Note 1:
Name
(1)
Pin
(1)
(1)
These registers are not available in 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and
PIC18LF26J53).
input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and
PIC18LF47J53).
TRISD7
LATD7
PORTD I/O SUMMARY (CONTINUED)
Bit 7
RD7
Function
PMD6
PMD7
RP23
RP24
RD6
RD7
(1)
(1)
TRISD6
LATD6
Bit 6
RD6
Setting
TRIS
1
0
1
0
1
0
1
0
1
0
1
0
I/O
TRISD5
O
O
O
O
O
O
LATD5
I
I
I
I
I
I
Bit 5
RD5
ST/TTL Parallel Master Port data in.
ST/TTL Parallel Master Port data in.
Type
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
Preliminary
TRISD4
LATD4
PORTD<6> data input.
LATD<6> data output.
Parallel Master Port data out.
Remappable Peripheral Pin 23 input.
Remappable Peripheral Pin 23 output.
PORTD<7> data input.
LATD<7> data output.
Parallel Master Port data out.
Remappable Peripheral Pin 24 input.
Remappable Peripheral Pin 24 output.
Bit 4
RD4
PIC18F47J53 FAMILY
TRISD3
LATD3
Bit 3
RD3
Description
TRISD2
LATD2
Bit 2
RD2
2
TRISD1
C/SMB = I
LATD1
Bit 1
RD1
DS39964B-page 157
2
C/SMBus
TRISD0
LATD0
Bit 0
RD0