PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 262

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J53 FAMILY
18.1.2
When operating in Output mode (the Compare or PWM
modes), the drivers for the CCPx pins can be optionally
configured as open-drain outputs. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor and allows the out-
put to communicate with external circuits without the
need for additional level shifters.
The open-drain output option is controlled by the
CCPxOD bits (ODCON1<7:0> and ODCON2<3:2>).
Setting the appropriate bit configures the pin for the
corresponding module for open-drain operation.
18.2
In Capture mode, the CCPR4H:CCPR4L register pair
captures the 16-bit value of the TMR1 or TMR3 register
when an event occurs on the CCP4 pin, RB4. An event
is defined as one of the following:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
FIGURE 18-1:
DS39964B-page 262
Note:
Capture Mode
OPEN-DRAIN OUTPUT OPTION
CCP5 Pin
CCP4 Pin
This block diagram uses CCP4 and CCP5 and their appropriate timers as an example. For details on all of
the CCP modules and their timer assignments, see Table 18-2 and Table 18-3.
CAPTURE MODE OPERATION BLOCK DIAGRAM
CCP5CON<3:0>
CCP4CON<3:0>
Prescaler
 1, 4, 16
Prescaler
 1, 4, 16
Q1:Q4
4
Edge Detect
Edge Detect
4
4
and
and
Set CCP4IF
Set CCP5IF
Preliminary
C4TSEL1
C4TSEL0
C4TSEL0
C4TSEL1
C5TSEL0
C5TSEL0
Counter mode, the capture operation may not work.
The event is selected by the mode select bits,
CCP4M<3:0> (CCP4CON<3:0>). When a capture is
made, the interrupt request flag bit, CCP4IF (PIR4<1>),
is set. (It must be cleared in software.) If another
capture occurs before the value in register, CCPR4, is
read, the old captured value is overwritten by the new
captured value.
Figure 18-1 shows the Capture mode block diagram.
18.2.1
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
18.2.2
For the available timers (1/3/5) to be used for the capture
feature, the used timers must be running in Timer mode
or Synchronized Counter mode. In Asynchronous
The timer to be used with each CCP module is selected
in the CCPTMRSx registers. (See Section 18.1.1 “CCP
Modules and Timer Resources”.)
Details of the timer assignments for the CCP modules
are given in Table 18-2 and Table 18-3.
Note:
CCP PIN CONFIGURATION
If RB4 is configured as a CCP4 output, a
write to the port causes a capture condition.
TIMER1/3/5 MODE SELECTION
TMR5
Enable
TMR1
Enable
TMR3
Enable
TMR1
Enable
CCPR5H
CCPR4H
TMR1H
TMR5H
TMR3H
TMR1H
 2010 Microchip Technology Inc.
CCPR5L
CCPR4L
TMR1L
TMR5L
TMR3L
TMR1L