PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 67

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.2
The Master Clear Reset (MCLR) pin provides a method
for triggering a hard external Reset of the device. A
Reset is generated by holding the pin low. PIC18
extended microcontroller devices have a noise filter in
the MCLR Reset path, which detects and ignores small
pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
5.3
A POR condition is generated on-chip whenever V
rises above a certain threshold. This allows the device
to start in the initialized state when V
operation.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k to 10 k) to V
eliminate external RC components usually needed to
create a POR delay.
When the device starts normal operation (i.e., exits the
Reset
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a Power-on
Reset occurs; it does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To capture multiple events, the user manually resets
the bit to ‘1’ in software following any POR.
5.4
The “F” devices in the PIC18F47J53 family incorporate
two types of BOR circuits: one which monitors
V
circuit can be active at a time. When in normal Run
mode, Idle or normal Sleep modes, the BOR circuit that
monitors V
to be held in BOR if V
(parameter D005). Once V
V
expiration of the Power-up Timer, with period, T
(parameter 33).
During Deep Sleep operation, the on-chip core voltage
regulator is disabled and V
V
DSBOREN bit (CONFIG3L<2> = 1), it will monitor V
If V
will be held in a Reset state similar to POR. All registers
will be set back to their POR Reset values and the con-
tents of the DSGPR0 and DSGPR1 holding registers
will be lost. Additionally, if any I/O pins had been
configured as outputs during Deep Sleep, these pins
will be tri-stated and the device will no longer be held in
 2010 Microchip Technology Inc.
DDCORE
BOR
SS
DD
. If the Deep Sleep BOR circuit is enabled by the
, the device will be held in Reset until the
drops below the V
condition),
Master Clear (MCLR)
Power-on Reset (POR)
Brown-out Reset (BOR)
and one which monitors V
DDCORE
is active and will cause the device
device
DDCORE
DSBOR
DDCORE
DDCORE
operating
threshold, the device
is allowed to drop to
drops below V
DD
DD
rises back above
. Only one BOR
is adequate for
DD
parameters
. This will
PWRT
BOR
Preliminary
DD
DD
.
PIC18F47J53 FAMILY
Deep Sleep. Once the V
above the V
voltage regulator achieves a V
V
normally, but the DS bit in the WDTCON register will
not be set. The device behavior will be similar to hard
cycling all power to the device.
On “LF” devices (ex: PIC18LF47J53), the V
BOR circuit is always disabled because the internal
core voltage regulator is disabled. Instead of monitor-
ing V
use the V
below the V
be disabled by setting the DSBOREN bit = 0.
The V
on “LF” devices, or on “F” devices while in Deep Sleep
with DSBOREN = 1. When enabled, the V
cuit is extremely low power (typ. 200nA) during normal
operation above ~2.3V on V
DSBOR arming level when the V
enabled, the device may begin to consume additional
current (typ. 50 A) as internal features of the circuit
power-up. The higher current is necessary to achieve
more accurate sensing of the V
device will not enter Reset until V
V
5.4.1
The BOR bit always resets to ‘0’ on any V
Brown-out Reset or Power-on Reset event. This makes
it difficult to determine if a Brown-out Reset event has
occurred just by reading the state of BOR alone. A
more reliable method is to simultaneously check the
state of both POR and BOR. This assumes that the
POR bit is reset to ‘1’ in software immediately after any
Power-on Reset event. If BOR is ‘0’ while POR is ‘1’, it
can be reliably assumed that a Brown-out Reset event
has occurred.
If the voltage regulator is disabled (LF device), the
V
the BOR bit cannot be used to determine a Brown-out
Reset event. The BOR bit is still cleared by a Power-on
Reset event.
BOR
DSBOR
DDCORE
, the device will begin executing code again
DDCORE
DD
threshold.
BOR circuit is enabled when DSBOREN = 1
DD
BOR functionality is disabled. In this case,
DSBOR
DETECTING BOR
, PIC18LF devices in this family can still
DSBOR
BOR circuit to monitor V
threshold. The V
threshold, and once the core
DD
DD
. If V
voltage recovers back
DDCORE
DD
DD
level. However, the
DD
DD
DD
DS39964B-page 67
drops below this
BOR circuit can
falls below the
BOR circuit is
DD
voltage above
DD
excursions
BOR cir-
DDCORE
DDCORE