PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 313

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

REGISTER 20-7:
 2010 Microchip Technology Inc.
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
GCEN
R/W-0
bit 7
2:
3:
(3)
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
If the I
(or writes to the SSPxBUF are disabled).
This bit is not implemented in I
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit
1 = Initiates Acknowledge sequence on SDAx and SCLx pins, and transmits ACKDT data bit;
0 = Acknowledge sequence Idle
RCEN: Receive Enable bit (Master Receive mode only)
1 = Enables Receive mode for I
0 = Receive Idle
PEN: Stop Condition Enable bit
1 = Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Stop condition Idle
RSEN: Repeated Start Condition Enable bit
1 = Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Repeated Start condition Idle
SEN: Start Condition Enable bit
1 = Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Start condition Idle
ACKSTAT
2
R/W-0
C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
automatically cleared by hardware
SSPxCON2: MSSPx CONTROL REGISTER 2 (I
(1, ACCESS FC5h; 2, F71h)
W = Writable bit
‘1’ = Bit is set
ACKDT
R/W-0
(1)
2
C Master mode.
ACKEN
(2)
(2)
2
C
R/W-0
Preliminary
(2)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
PIC18F47J53 FAMILY
RCEN
R/W-0
(3)
(2)
(2)
(1)
2
PEN
R/W-0
C™ MASTER MODE)
(2)
x = Bit is unknown
RSEN
R/W-0
(2)
DS39964B-page 313
SEN
R/W-0
bit 0
(2)