PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 65

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.0
The PIC18F47J53 family of devices differentiates
among various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
i)
j)
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers.
FIGURE 5-1:
 2010 Microchip Technology Inc.
V
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog
execution)
Configuration Mismatch (CM)
Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
Deep Sleep Reset
Note 1: The V
MCLR
DDCORE
V
DD
RESET
2: The V
Deep Sleep Reset
Pointer
Configuration bit. On “F” devices, the V
CONFIG3L<DSBOREN>.
Sleep mode. The V
Stack
Configuration Word Mismatch
PWRT
Timer
Brown-out
INTRC
( )_IDLE
V
Time-out
32 ms
Reset
DD
Detect
DD
DDCORE
WDT
Sleep
Rise
monitoring BOR circuit can be enabled or disabled on “LF” devices based on the CONFIG3L<DSBOREN>
External Reset
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
(1)
RESET Instruction
(WDT)
monitoring BOR circuit is only implemented on “F” devices. It is always used, except while in Deep
POR Pulse
PWRT
DDCORE
Brown-out
11-Bit Ripple Counter
Reset
Reset
(2)
monitoring BOR circuit has a trip point threshold of V
66 ms
(during
DD
Preliminary
monitoring BOR circuit is only enabled during Deep Sleep mode by
PIC18F47J53 FAMILY
For information on WDT Resets, see Section 28.2
“Watchdog Timer (WDT)”. For Stack Reset events,
see Section 6.1.4.4 “Stack Full and Underflow
Resets” and for Deep Sleep mode, see Section 4.6
“Deep Sleep Mode”.
Figure 5-1 provides a simplified block diagram of the
on-chip Reset circuit.
5.1
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the register
indicate that a specific Reset event has occurred. In
most cases, these bits can only be set by the event and
must be cleared by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 5.7 “Reset State of
Registers”.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 9.0 “Interrupts”.
RCON Register
BOR
(parameter D005).
S
R
Q
DS39964B-page 65
Chip_Reset