PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 389

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

The BDnSTAT byte of the BDT should always be the
last byte updated when preparing to arm an endpoint.
The SIE will clear the UOWN bit when a transaction
has completed.
No hardware mechanism exists to block access when
the UOWN bit is set. Thus, unexpected behavior can
occur if the microcontroller attempts to modify memory
when the SIE owns it. Similarly, reading such memory
may produce inaccurate data until the USB peripheral
returns ownership to the microcontroller.
23.4.1.2
When UOWN = 0, the microcontroller core owns the
BD. At this point, the other seven bits of the register
take on control functions.
The
(BDnSTAT<3>), controls data toggle parity checking.
Setting DTSEN enables data toggle synchronization by
the SIE. When enabled, it checks the data packet’s par-
ity against the value of DTS (BDnSTAT<6>). If a packet
arrives with an incorrect synchronization, the data will
essentially be ignored. It will not be written to the USB
RAM and the USB transfer complete interrupt flag will
not be set. The SIE will send an ACK token back to the
host to Acknowledge receipt, however. The effects of
the DTSEN bit on the SIE are summarized in
Table 23-1.
TABLE 23-1:
 2010 Microchip Technology Inc.
DATA0
DATA1
DATA0
DATA1
Either
Either, with error
Legend: x = don’t care
OUT Packet
from Host
Data
BDnSTAT Register (CPU Mode)
Toggle
EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION
Sync
DTSEN
BDnSTAT Settings
1
1
1
1
0
x
Enable
DTS
0
0
1
1
x
x
bit,
DTSEN
Handshake
Preliminary
ACK
ACK
ACK
ACK
ACK
NAK
Device Response after Receiving Packet
PIC18F47J53 FAMILY
UOWN
The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides
support for control transfers, usually one-time stalls on
Endpoint 0. It also provides support for the
SET_FEATURE/CLEAR_FEATURE commands speci-
fied in Chapter 9 of the USB Specification; typically,
continuous STALLs to any endpoint other than the
default control endpoint.
The BSTALL bit enables buffer stalls. Setting BSTALL
causes the SIE to return a STALL token to the host if a
received token would use the BD in that location. The
EPSTALL bit in the corresponding UEPn Control
register is set and a STALL interrupt is generated when
a STALL is issued to the host. The UOWN bit remains
set and the BDs are not changed unless a SETUP
token is received. In this case, the STALL condition is
cleared and the ownership of the BD is returned to the
microcontroller core.
The BCx<9:8> bits (BDnSTAT<1:0>) store the two
most significant digits of the SIE byte count. The lower
8 digits are stored in the corresponding BDnCNT regis-
ter. See Section 23.4.2 “BD Byte Count” for more
information.
0
1
1
0
0
1
TRNIF
1
0
0
1
1
0
BDnSTAT and USTAT Status
Not Updated
Not Updated
Not Updated
Updated
Updated
Updated
DS39964B-page 389