PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 63

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

A series resistor between RA0 and the external
capacitor provides overcurrent protection for the
RA0/AN0/C1INA/ULPWU/RP0 pin and can allow for
software calibration of the time-out (see Figure 4-9).
FIGURE 4-9:
A timer can be used to measure the charge time and
discharge time of the capacitor. The charge time can
then be adjusted to provide the desired interrupt delay.
This technique will compensate for the affects of
temperature, voltage and component accuracy. The
ULPWU peripheral can also be configured as a simple
Programmable
temperature sensor.
TABLE 4-2:
 2010 Microchip Technology Inc.
Note 1:
Register
PMDIS3
PMDIS2
PMDIS1
PMDIS0
Note:
CCP10MD
ECCP3MD ECCP2MD ECCP1MD UART2MD UART1MD
Not implemented on 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53).
RA0
For more information, refer to AN879,
“Using the Microchip Ultra Low-Power
Wake-up
(DS00879).
PSPMD
Bit 7
—
Low-Voltage
LOW-POWER MODE REGISTERS
(1)
SERIAL RESISTOR
CTMUMD
Module”
CCP9MD
TMR8MD
Bit 6
R
1
Detect
application
RTCCMD
CCP8MD
C
Bit 5
1
—
(LVD)
TMR6MD
TMR4MD
CCP7MD
note
Bit 4
Preliminary
or
CCP6MD
TMR5MD
TMR3MD
Bit 3
PIC18F47J53 FAMILY
4.8
All peripheral modules (except for I/O ports) also have
a second control bit that can disable their functionality.
These bits, known as the Peripheral Module Disable
(PMDISx) bits, are generically named “xxxMD” (using
“xxx” as the mnemonic version of the module’s name).
These bits are located in the PMDISx special function
registers. In contrast to the module enable bits (gener-
ically named “xxxEN” and located in bit position seven
of the control registers), the PMDISx bits must be set
(= 1) to disable the modules.
While the PMD and module enable bits both disable a
peripheral’s functionality, the PMD bit completely shuts
down the peripheral, effectively powering down all
circuits and removing all clock sources. This has the
additional effect of making any of the module’s control
and buffer registers, mapped in the SFR space,
unavailable for operations. Essentially, the peripheral
ceases to exist until the PMD bit is cleared.
This differs from using the module enable bit, which
allows the peripheral to be reconfigured and buffer reg-
isters
operations are disabled.
The
power-sensitive applications. In these cases, the bits
can be set before the main body of the application to
remove peripherals that will not be needed at all.
PMDISx
CCP5MD
CMP3MD
TMR2MD
SPI2MD
preloaded,
Bit 2
Peripheral Module Disable
bits
CCP4MD
CMP2MD
TMR1MD
SPI1MD
Bit 1
even
are
most
when
CMP1MD
ADCMD
Bit 0
—
—
useful
DS39964B-page 63
the
0000 000–
–0–0 0000
0000 000–
0000 0000
POR, BOR
peripheral’s
Value on
in
highly