PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 547

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 31-25: I
 2010 Microchip Technology Inc.
100
101
102
103
90
91
106
107
92
109
110
D102
Note 1:
Param.
No.
2:
T
T
T
T
T
T
T
T
T
T
T
C
Symbol
SU
SU
SU
AA
HIGH
LOW
R
F
HD
HD
BUF
B
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
A Fast mode I
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal.
If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, T
max. + T
released.
:
:
:
:
:
STA
DAT
STO
STA
DAT
2
SU
Clock High Time
Clock Low Time
SDAx and SCLx Rise Time 100 kHz mode
SDAx and SCLx Fall Time 100 kHz mode
Start Condition Setup Time 100 kHz mode
Start Condition Hold Time
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time 100 kHz mode
Output Valid from Clock
Bus Free Time
Bus Capacitive Loading
C™ BUS DATA REQUIREMENTS (SLAVE MODE)
:
DAT
2
C™ bus device can be used in a Standard mode I
= 1000 + 250 = 1250 ns (according to the Standard mode I
Characteristic
100 kHz mode
400 kHz mode
MSSP modules
100 kHz mode
400 kHz mode
MSSP modules
400 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
Preliminary
PIC18F47J53 FAMILY
20 + 0.1 C
20 + 0.1 C
1.5 T
1.5 T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
CY
CY
2
C bus system, but the requirement, T
B
B
3500
1000
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C bus specification), before the SCLx line is
Units
pF
s
s
s
s
ns
ns
ns
ns
s
s
s
s
ns
s
ns
ns
s
s
ns
ns
s
s
C
10 to 400 pF
C
10 to 400 pF
Only relevant for Repeated
Start condition
After this period, the first clock
pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission can
start
B
B
is specified to be from
is specified to be from
Conditions
DS39964B-page 547
SU
:
DAT
 250 ns,
R