PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 289

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.4.8
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCPx pin is driving a value, it will con-
tinue to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from HFINTOSC
and the postscaler may not be immediately stable.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCPx module without change.
19.4.8.1
If the Fail-Safe Clock Monitor (FSCM) is enabled, a clock
failure will force the device into the power-managed
RC_RUN mode and the OSCFIF bit of the PIR2 register
TABLE 19-4:
 2010 Microchip Technology Inc.
INTCON
RCON
PIR1
PIR2
PIR4
PIE1
PIE2
PIE4
IPR1
IPR2
IPR4
TRISB
TRISC
TRISE
TMR1H
TMR1L
TMR2
TMR3H
TMR3L
TMR4
TMR6
TMR8
PR2
PR4
PR6
PR8
T1CON
T2CON
T3CON
T4CON
T6CON
File Name
OPERATION IN POWER-MANAGED
MODES
Operation with Fail-Safe
Clock Monitor (FSCM)
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer3 Register High Byte
Timer3 Register Low Byte
Timer4 Register
Timer6 Register
Timer8 Register
Timer2 Period Register
Timer4 Period Register
Timer6 Period Register
Timer8 Period Register
TMR1CS1
TMR3CS1
GIE/GIEH
REGISTERS ASSOCIATED WITH ECCP1/2/3 MODULE AND
TIMER1/2/3/4/6/8
CCP10IF
CCP10IE
CCP10IP
OSCFIE
OSCFIP
OSCFIF
TRISC7
TRISB7
PMPIE
PMPIP
PMPIF
RDPU
IPEN
Bit 7
—
—
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
T4OUTPS3 T4OUTPS2
T6OUTPS3 T6OUTPS2
TMR1CS0
TMR3CS0
PEIE/GIEL
CCP9IE
CCP9IP
CCP9IF
TRISB6
TRISC6
CM2IE
CM2IP
CM2IF
REPU
ADIE
ADIP
ADIF
Bit 6
—
T1CKPS1
T3CKPS1
TMR0IE
CCP8IF
CCP8IE
CCP8IP
TRISB5
CM1IF
CM1IE
CM1IP
RC1IF
RC1IE
RC1IP
Bit 5
CM
—
—
Preliminary
T4OUTPS1 T4OUTPS0
T6OUTPS1 T6OUTPS0
T1CKPS0
T3CKPS0
CCP7IF
CCP7IE
CCP7IP
TRISB4
INT0IE
USBIE
USBIP
USBIF
TX1IF
TX1IE
TX1IP
Bit 4
RI
—
—
PIC18F47J53 FAMILY
will be set. The ECCPx will then be clocked from the
internal oscillator clock source, which may have a
different clock frequency than the primary clock.
19.4.9
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the ECCP registers to their
Reset states.
This forces the ECCP module to reset to a state
compatible with previous, non-enhanced CCP modules
used on other PIC18 and PIC16 devices.
T1OSCEN
T3OSCEN
CCP6IF
SSP1IE
CCP6IE
SSP1IP
CCP6IP
TRISB3
SSP1IF
BCL1IF
BCL1IE
BCL1IP
RBIE
Bit 3
TO
—
—
EFFECTS OF A RESET
TMR4ON
TMR6ON
TMR2ON
T1SYNC
T3SYNC
TMR0IF
CCP1IE
CCP5IE
CCP1IP
CCP5IP
CCP1IF
HLVDIF
CCP5IF
HLVDIE
HLVDIP
TRISB2
TRISC2
TRISE2
Bit 2
PD
T4CKPS1
T6CKPS1
T2CKPS1
TMR2IF
TMR3IF
TMR2IE
TMR3IE
CCP4IE
TMR2IP
TMR3IP
CCP4IP
CCP4IF
TRISB1
TRISC1
TRISE1
INT0IF
RD16
RD16
Bit 1
POR
DS39964B-page 289
T4CKPS0
T6CKPS0
T2CKPS0
TMR1ON
TMR3ON
TMR1IF
TMR1IE
CCP2IE
CCP3IE
TMR1IP
CCP2IP
CCP3IP
CCP2IF
CCP3IF
TRISB0
TRISC0
TRISE0
RBIF
Bit 0
BOR