PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 392

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J53 FAMILY
23.4.4
An endpoint is defined to have a ping-pong buffer when
it has two sets of BD entries: one set for an Even
transfer and one set for an Odd transfer. This allows the
CPU to process one BD while the SIE is processing the
other BD. Double-buffering BDs in this way allows for
maximum throughput to/from the USB.
The USB module supports four modes of operation:
• No ping-pong support
• Ping-pong buffer support for OUT Endpoint 0 only
• Ping-pong buffer support for all endpoints
• Ping-pong buffer support for all other endpoints
The ping-pong buffer settings are configured using the
PPB<1:0> bits in the UCFG register.
The USB module keeps track of the Ping-Pong Pointer
individually for each endpoint. All pointers are initially
reset to the Even BD when the module is enabled. After
FIGURE 23-6:
DS39964B-page 392
D00h
D7Fh
DFFh
except Endpoint 0
Note:
Maximum Memory
Used: 128 bytes
Maximum BDs:
32 (BD0 to BD31)
PPB<1:0> = 00
No Ping-Pong
Data RAM
Available
Buffers
as
PING-PONG BUFFERING
Memory area is not shown to scale.
EP0 OUT
Descriptor
EP0 IN
Descriptor
EP1 OUT
Descriptor
EP1 IN
Descriptor
EP15 IN
Descriptor
BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES
D00h
D83h
DFFh
Ping-Pong Buffer
PPB<1:0> = 01
Maximum Memory
Used: 132 bytes
Maximum BDs:
33 (BD0 to BD32)
on EP0 OUT
Data RAM
Available
as
EP0 OUT Even
Descriptor
EP0 OUT Odd
Descriptor
EP0 IN
Descriptor
EP1 OUT
Descriptor
EP1 IN
Descriptor
EP15 IN
Descriptor
Preliminary
DFFh
D00h
Ping-Pong Buffers
PPB<1:0> = 10
Maximum Memory
Used: 256 bytes
Maximum BDs: 6
4 (BD0 to BD63)
on all EPs
the completion of a transaction (UOWN cleared by the
SIE), the pointer is toggled to the Odd BD. After the
completion of the next transaction, the pointer is
toggled back to the Even BD and so on.
The Even/Odd status of the last transaction is stored in
the PPBI bit of the USTAT register. The user can reset
all Ping-Pong Pointers to Even using the PPBRST bit.
Figure 23-6 shows the four different modes of
operation and how USB RAM is filled with the BDs.
BDs have a fixed relationship to a particular endpoint,
depending on the buffering configuration. Table 23-2
provides the mapping of BDs to endpoints. This
relationship also means that gaps may occur in the
BDT if endpoints are not enabled contiguously. This,
theoretically, means that the BDs for disabled
endpoints could be used as buffer space. In practice,
users should avoid using such spaces in the BDT
unless a method of validating BD addresses is
implemented.
EP0 OUT Even
Descriptor
EP0 OUT Odd
Descriptor
EP0 IN Even
Descriptor
EP0 IN Odd
Descriptor
EP1 OUT Even
Descriptor
EP1 OUT Odd
Descriptor
EP1 IN Odd
Descriptor
EP15 IN Odd
Descriptor
EP1 IN Even
Descriptor
DF7h
DFFh
D00h
 2010 Microchip Technology Inc.
Ping-Pong Buffers
on all other EPs
PPB<1:0> = 11
Maximum Memory
Used: 248 bytes
Maximum BDs:
62 (BD0 to BD61)
except EP0
Data RAM
Available
as
EP0 OUT
Descriptor
EP0 IN
Descriptor
EP1 OUT Even
Descriptor
EP1 OUT Odd
Descriptor
EP1 IN Odd
Descriptor
EP15 IN Odd
Descriptor
EP1 IN Even
Descriptor