PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 335

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.5.10
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPxBUF register. This action will
set the Buffer Full flag bit, BF, and allow the BRG to
begin counting and start the next transmission. Each bit
of address/data will be shifted out onto the SDAx pin
after the falling edge of SCLx is asserted (see data hold
time specification, parameter 106). SCLx is held low for
one BRG rollover count (T
before SCLx is released high (see data setup time
specification, parameter 107). When the SCLx pin is
released high, it is held that way for T
The data on the SDAx pin must remain stable for that
duration, and some hold time, after the next falling
edge of SCLx. After the eighth bit is shifted out (the fall-
ing edge of the eighth clock), the BF flag is cleared and
the master releases SDAx. This allows the slave device
being addressed to respond with an ACK bit during the
ninth bit time if an address match occurred or if data
was received properly. The status of ACK is written into
the ACKDT bit on the falling edge of the ninth clock.
If the master receives an Acknowledge, the Acknowl-
edge Status bit, ACKSTAT, is cleared; if not, the bit is
set. After the ninth clock, the SSPxIF bit is set and the
master clock (BRG) is suspended until the next data
byte is loaded into the SSPxBUF, leaving SCLx low and
SDAx unchanged (Figure 20-23).
After the write to the SSPxBUF, each bit of the address
will be shifted out on the falling edge of SCLx until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
deassert the SDAx pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDAx pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT status bit
(SSPxCON2<6>). Following the falling edge of the
ninth clock transmission of the address, the SSPxIF
flag is set, the BF flag is cleared and the BRG is turned
off until another write to the SSPxBUF takes place,
holding SCLx low and allowing SDAx to float.
20.5.10.1
In Transmit mode, the BF bit (SSPxSTAT<0>) is set
when the CPU writes to SSPxBUF and is cleared when
all eight bits are shifted out.
20.5.10.2
If the user writes the SSPxBUF when a transmit is
already in progress (i.e., SSPxSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur) after
2 T
within 2 T
updated. This may result in a corrupted transfer.
 2010 Microchip Technology Inc.
CY
after the SSPxBUF write. If SSPxBUF is rewritten
CY
I
TRANSMISSION
2
, the WCOL bit is set and SSPxBUF is
C MASTER MODE
BF Status Flag
WCOL Status Flag
BRG
). Data should be valid
BRG
.
Preliminary
PIC18F47J53 FAMILY
The user should verify that the WCOL bit is clear after
each write to SSPxBUF to ensure the transfer is correct.
In all cases, WCOL must be cleared in software.
20.5.10.3
In Transmit mode, the ACKSTAT bit (SSPxCON2<6>)
is cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call)
or when the slave has properly received its data.
20.5.11
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPxCON2<3>).
The BRG begins counting, and on each rollover, the
state of the SCLx pin changes (high-to-low/low-to-high)
and data is shifted into the SSPxSR. After the falling
edge of the eighth clock, the receive enable flag is
automatically cleared, the contents of the SSPxSR are
loaded into the SSPxBUF, the BF flag bit is set, the
SSPxIF flag bit is set and the BRG is suspended from
counting, holding SCLx low. The MSSP is now in an
Idle state awaiting the next command. When the buffer
is read by the CPU, the BF flag bit is automatically
cleared. The user can then send an Acknowledge bit at
the end of reception by setting the Acknowledge
Sequence Enable bit, ACKEN (SSPxCON2<4>).
20.5.11.1
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPxBUF from SSPxSR. It
is cleared when the SSPxBUF register is read.
20.5.11.2
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPxSR and the BF flag bit is
already set from a previous reception.
20.5.11.3
If users write the SSPxBUF when a receive is already
in progress (i.e., SSPxSR is still shifting in a data byte),
the WCOL bit is set and the contents of the buffer are
unchanged (the write does not occur).
Note:
I
The MSSP module must be in an inactive
state before the RCEN bit is set or the
RCEN bit will be disregarded.
2
ACKSTAT Status Flag
C MASTER MODE RECEPTION
BF Status Flag
SSPOV Status Flag
WCOL Status Flag
DS39964B-page 335