PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 57

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.6.5
The Deep Sleep module contains a dedicated Deep Sleep
BOR (DSBOR) circuit. This circuit may be optionally
enabled through the DSBOREN Configuration bit.
The DSBOR circuit monitors the V
voltage. The behavior of the DSBOR circuit is
described in Section 5.4 “Brown-out Reset (BOR)”.
4.6.6
The RTCC can operate uninterrupted during Deep
Sleep mode. It can wake the device from Deep Sleep
by configuring an alarm.
The RTCC clock source is configured with the
RTCOSC bit (CONFIG3L<1>). The available reference
clock sources are the INTRC and T1OSC/T1CKI. If the
INTRC is used, the RTCC accuracy will directly depend
on the INTRC tolerance.For more information on
configuring the RTCC peripheral, see Section 17.0
“Real-Time Clock and Calendar (RTCC)”.
4.6.7
This section gives the typical sequence for using the Deep
Sleep mode. Optional steps are indicated and additional
information is given in notes at the end of the procedure.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If using an RTCC alarm for wake-up, wait until
11. Enter Deep Sleep mode by setting the DSEN bit
12. Once a wake-up event occurs, the device will
13. Determine if the device exited Deep Sleep by
 2010 Microchip Technology Inc.
Enable DSWDT (optional).
Configure the DSWDT clock source (optional).
Enable DSBOR (optional).
Enable RTCC (optional).
Configure the RTCC peripheral (optional).
Configure the ULPWU peripheral (optional).
Enable the INT0 Interrupt (optional).
Context save SRAM data by writing to the
DSGPR0 and DSGPR1 registers (optional).
Set the REGSLP bit (WDTCON<7>) and clear
the IDLEN bit (OSCCON<7>).
the RTCSYNC bit (RTCCFG<4>) is clear.
(DSCONH<7>) and issuing a SLEEP instruction.
These two instructions must be executed back
to back.
perform a POR Reset sequence. Code execution
resumes at the device’s Reset vector.
reading the Deep Sleep bit, DS (WDTCON<3>).
This bit will be set if there was an exit from Deep
Sleep mode.
DEEP SLEEP BROWN-OUT RESET
(DSBOR)
RTCC PERIPHERAL AND DEEP
SLEEP
TYPICAL DEEP SLEEP SEQUENCE
(3)
(1)
(1)
DD
supply rail
(3)
(4)
(2)
Preliminary
PIC18F47J53 FAMILY
14. Clear the Deep Sleep bit, DS (WDTCON<3>).
15. Determine the wake-up source by reading the
16. Determine if a DSBOR event occurred during
17. Read the DSGPR0 and DSGPR1 context save
18. Clear the RELEASE bit (DSCONL<0>).
4.6.8
If during Deep Sleep, the device is subjected to
unusual operating conditions, such as an Electrostatic
Discharge (ESD) event, it is possible that internal cir-
cuit states used by the Deep Sleep module could
become corrupted. If this were to happen, the device
may exhibit unexpected behavior, such as a failure to
wake back up.
In order to prevent this type of scenario from occurring,
the
self-monitoring capability. During Deep Sleep, critical
internal nodes are continuously monitored in order to
detect possible Fault conditions (which would not
ordinarily occur). If a Fault condition is detected, the
circuitry will set the DSFLT status bit (DSWAKEL<7>)
and automatically wake the microcontroller from Deep
Sleep, causing a POR Reset.
During Deep Sleep, the Fault detection circuitry is
always enabled and does not require any specific
configuration prior to entering Deep Sleep.
Note 1: DSWDT
DSWAKEH and DSWAKEL registers.
Deep Sleep mode by reading the DSBOR bit
(DSCONL<1>).
registers (optional).
Deep
2: The DSWDT and RTCC clock sources
3: For more information, see Section 17.0
4: For more information on configuring this
DEEP SLEEP FAULT DETECTION
through the devices’ Configuration bits.
For more information, see Section 28.1
“Configuration Bits”.
are selected through the devices’ Con-
figuration bits. For more information, see
Section 28.1 “Configuration Bits”.
“Real-Time
(RTCC)”.
peripheral,
Low-Power Wake-up”.
Sleep
module
and
see
Clock
DSBOR
Section 4.7
includes
DS39964B-page 57
and
are
Calendar
automatic
enabled
“Ultra