PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 193

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11.3
In its Master modes, the PMP module provides an 8-bit
data bus, up to 16 bits of address, and all the necessary
control signals to operate a variety of external parallel
devices, such as memory devices, peripherals and
slave microcontrollers. To use the PMP as a master,
the module must be enabled (PMPEN = 1) and the
mode must be set to one of the two possible Master
modes (PMMODEH<1:0> = 10 or 11).
Because there are a number of parallel devices with a
variety of control methods, the PMP module is designed
to be extremely flexible to accommodate a range of
configurations. Some of these features include:
• 8-Bit and 16-Bit Data modes on an 8-bit data bus
• Configurable address/data multiplexing
• Up to two chip select lines
• Up to 16 selectable address lines
• Address auto-increment and auto-decrement
• Selectable polarity on all control lines
• Configurable Wait states at different stages of the
11.3.1
Multiple control bits are used to configure the presence
or absence of control and address signals in the
module. These bits are PTBEEN, PTWREN, PTRDEN
and PTEN<15:0>. They give the user the ability to con-
serve pins for other functions and allow flexibility to
control the external address. When any one of these
bits is set, the associated function is present on its
associated pin; when clear, the associated pin reverts
to its defined I/O port function.
Setting a PTENx bit will enable the associated pin as
an address pin and drive the corresponding data
contained in the PMADDR register. Clearing a PTENx
bit will force the pin to revert to its original I/O function.
For the pins configured as chip select (PMCS1 or
PMCS2) with the corresponding PTENx bit set, the
PTEN0 and PTEN1 bits will also control the PMALL
and PMALH signals. When multiplexing is used, the
associated address latch signals should be enabled.
11.3.2
The PMP module supports two distinct read/write
signaling methods. In Master Mode 1, read and write
strobes are combined into a single control line,
PMRD/PMWR. A second control line, PMENB, deter-
mines when a read or write action is to be taken. In
Master Mode 2, separate read and write strobes
(PMRD and PMWR) are supplied on separate pins.
All control signals (PMRD, PMWR, PMBE, PMENB,
PMAL and PMCSx) can be individually configured as
either positive or negative polarity. Configuration is
controlled by separate bits in the PMCONL register.
Note that the polarity of control signals that share the
 2010 Microchip Technology Inc.
read/write cycle
MASTER PORT MODES
PMP AND I/O PIN CONTROL
READ/WRITE-CONTROL
Preliminary
PIC18F47J53 FAMILY
same output pin (for example, PMWR and PMENB) are
controlled by the same bit; the configuration depends
on which Master Port mode is being used.
11.3.3
The PMP supports data widths of both 8 bits and
16 bits. The data width is selected by the MODE16 bit
(PMMODEH<2>). Because the data path into and out
of the module is only 8 bits wide, 16-bit operations are
always handled in a multiplexed fashion, with the Least
Significant Byte (LSB) of data being presented first. To
differentiate data bytes, the byte enable control strobe,
PMBE, is used to signal when the Most Significant Byte
(MSB) of data is being presented on the data lines.
11.3.4
In either of the Master modes (PMMODEH<1:0> = 1x),
the user can configure the address bus to be multiplexed
together with the data bus. This is accomplished by
using the ADRMUX<1:0> bits (PMCONH<4:3>). There
are three address multiplexing modes available. Typical
pinout configurations for these modes are displayed in
Figure 11-9, Figure 11-10 and Figure 11-11.
In Demultiplexed mode (PMCONH<4:3> = 00), data and
address information are completely separated. Data bits
are presented on PMD<7:0> and address bits are
presented on PMADDRH<6:0> and PMADDRL<7:0>.
In Partially Multiplexed mode (PMCONH<4:3> = 01), the
lower eight bits of the address are multiplexed with the
data pins on PMD<7:0>. The upper eight bits of the
address are unaffected and are presented on
PMADDRH<6:0>. The PMA0 pin is used as an address
latch and presents the Address Latch Low (PMALL)
enable strobe. The read and write sequences are
extended by a complete CPU cycle during which the
address is presented on the PMD<7:0> pins.
In Fully Multiplexed mode (PMCONH<4:3> = 10), the
entire 16 bits of the address are multiplexed with the
data pins on PMD<7:0>. The PMA0 and PMA1 pins are
used to present Address Latch Low (PMALL) enable
and Address Latch High (PMALH) enable strobes,
respectively. The read and write sequences are
extended by two complete CPU cycles. During the first
cycle, the lower eight bits of the address are presented
on the PMD<7:0> pins with the PMALL strobe active.
During the second cycle, the upper eight bits of the
address are presented on the PMD<7:0> pins with the
PMALH strobe active. In the event the upper address
bits are configured
corresponding address bits are automatically forced
to ‘0’.
DATA WIDTH
ADDRESS MULTIPLEXING
as chip select
DS39964B-page 193
pins,
the