PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 184

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J53 FAMILY
REGISTER 11-5:
REGISTER 11-6:
DS39964B-page 184
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-2
bit 1-0
Note 1:
PTEN15
PTEN7
R/W-0
R/W-0
This register is only available on 44-pin devices.
This register is only available on 44-pin devices.
PTEN<15:14>: PMCS1 Port Enable bits
1 = PMA<15:14> function as either PMA<15:14> or PMCS2 and PMCS1
0 = PMA<15:14> function as port I/O
PTEN<13:8>: PMP Address Port Enable bits
1 = PMA<13:8> function as PMP address lines
0 = PMA<13:8> function as port I/O
PTEN<7:2>: PMP Address Port Enable bits
1 = PMA<7:2> function as PMP address lines
0 = PMA<7:2> function as port I/O
PTEN<1:0>: PMALH/PMALL Strobe Enable bits
1 = PMA<1:0> function as either PMA<1:0> or PMALH and PMALL
0 = PMA<1:0> pads functions as port I/O
PTEN14
PTEN6
R/W-0
R/W-0
PMEH: PARALLEL PORT ENABLE REGISTER HIGH BYTE (BANKED F57h)
PMEL: PARALLEL PORT ENABLE REGISTER LOW BYTE (BANKED F56h)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
PTEN13
PTEN5
R/W-0
R/W-0
PTEN12
PTEN4
R/W-0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PTEN11
PTEN3
R/W-0
R/W-0
PTEN10
PTEN2
R/W-0
R/W-0
 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
PTEN1
PTEN9
R/W-0
R/W-0
PTEN8
PTEN0
R/W-0
R/W-0
(1)
(1)
bit 0
bit 0