PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 382

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

associated internal and/or external hardware must be
PIC18F47J53 FAMILY
The PPBRST bit (UCON<6>) controls the Reset status
when Double-Buffering mode (ping-pong buffering) is
used. When the PPBRST bit is set, all Ping-Pong
Buffer Pointers are set to the Even buffers. PPBRST
has to be cleared by firmware. This bit is ignored in
buffering modes not using ping-pong buffering.
The PKTDIS bit (UCON<4>) is a flag indicating that the
SIE has disabled packet transmission and reception.
This bit is set by the SIE when a SETUP token is
received to allow setup processing. This bit cannot be
set by the microcontroller, only cleared; clearing it
allows the SIE to continue transmission and/or
reception. Any pending events within the Buffer
Descriptor Table (BDT) will still be available, indicated
within the USTAT register’s FIFO buffer.
The RESUME bit (UCON<2>) allows the peripheral to
perform a remote wake-up by executing resume
signaling. To generate a valid remote wake-up,
firmware must set RESUME for 10 ms and then clear
the bit. For more information on resume signaling, see
Sections 7.1.7.5, 11.4.4 and 11.9 in the USB
2.0 Specification.
The SUSPND bit (UCON<1>) places the module and
supporting circuitry in a low-power mode. The input
clock to the SIE is also disabled. This bit should be set
by the software in response to an IDLEIF interrupt. It
should be reset by the microcontroller firmware after an
ACTVIF interrupt is observed. When this bit is active,
the device remains attached to the bus but the trans-
ceiver outputs remain Idle. The voltage on the V
may vary depending on the value of this bit. Setting this
bit before a IDLEIF request will result in unpredictable
bus behavior.
23.2.2
Prior to communicating over USB, the module’s
configured. Most of the configuration is performed with
the UCFG register (Register 23-2).The UFCG register
contains most of the bits that control the system level
behavior of the USB module. These include:
• Bus Speed (full speed versus low speed)
• On-Chip Pull-up Resistor Enable
• On-Chip Transceiver Enable
• Ping-Pong Buffer Usage
DS39964B-page 382
Note:
While in Suspend mode, a typical
bus-powered USB device is limited to
2.5 mA of current. This is the complete
current which may be drawn by the PIC
device and its supporting circuitry. Care
should be taken to assure minimum
current draw when the device enters
Suspend mode.
USB CONFIGURATION REGISTER
(UCFG)
USB
Preliminary
pin
The UCFG register also contains two bits, which aid in
module testing, debugging and USB certifications.
These bits control output enable state monitoring and
eye pattern generation.
23.2.2.1
The USB peripheral has a built-in, USB 2.0, full-speed
and low-speed capable transceiver, internally con-
nected to the SIE. This feature is useful for low-cost,
single chip applications. The UTRDIS bit (UCFG<3>)
controls the transceiver; it is enabled by default
(UTRDIS = 0). The FSEN bit (UCFG<2>) controls the
transceiver speed; setting the bit enables full-speed
operation.
The on-chip USB pull-up resistors are controlled by the
UPUEN bit (UCFG<4>). They can only be selected
when the on-chip transceiver is enabled.
The internal USB transceiver obtains power from the
V
cations, V
between 3.0V and 3.6V. The best electrical signal
quality is obtained when a 3.3V supply is used and
locally bypassed with a high quality ceramic capacitor
(ex: 0.1 F). The capacitor should be placed as close
as possible to the V
V
module is not used, but RC4 or RC5 are used as
general purpose inputs, V
to a power source (such as V
for the RC4 and RC5 pins are dependent upon the
V
The D+ and D- signal lines can be routed directly to
their respective pins on the USB connector or cable (for
hard-wired applications). No additional resistors,
capacitors or magnetic components are required as the
D+ and D- drivers have controlled slew rate and output
impedance
characteristic impedance of the USB cable.
In order to achieve optimum USB signal quality, the D+
and D- traces between the microcontroller and USB
connector (or cable) should be less than 19 cm long.
Both traces should be equal in length and they should
be routed parallel to each other. Ideally, these traces
should be designed to have a characteristic impedance
matching that of the USB cable.
USB
USB
USB
Note:
pin. In order to meet USB signalling level specifi-
supply level.
should always be maintained  V
USB
The USB speed, transceiver and pull-up
should only be configured during the
module setup phase. It is not recom-
mended to switch these settings while the
module is enabled.
Internal Transceiver
must be supplied with a voltage source
intended
USB
 2010 Microchip Technology Inc.
and V
USB
to
DD
should still be connected
SS
). The input thresholds
pins.
match
DD
. If the USB
with
the