PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 149

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 10-5:
 2010 Microchip Technology Inc.
RB0/AN12/
C3IND/INT0/
RP3
RB1/AN10/
C3INC/PMBE/
RTCC/
RP4
RB2/AN8/
C2INC/CTED1/
PMA3/VMO/
REFO/RP5
RB3/AN9/
C3INA/CTED2/
PMA2/VPO/
RP6
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
Note 1:
2:
3:
Pin
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting
the appropriate bits in the ANCON1 register.
All other pin functions are disabled when ICSP™ or ICD is enabled.
Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
PORTB I/O SUMMARY
Function
PMBE
PMA3
PMA2
CTED1
CTED2
C3IND
C3INC
C2INC
C3INA
RTCC
REFO
AN12
AN10
VMO
INT0
VPO
RB0
RP3
RB1
RP4
RB2
AN8
RP5
RB3
AN9
RP6
(3)
(3)
(3)
Setting
TRIS
1
0
1
1
1
1
0
1
0
1
1
x
0
1
0
1
0
1
1
1
x
0
0
1
0
0
1
1
1
1
x
0
1
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
TTL
DIG
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
Preliminary
PORTB<0> data input; weak pull-up when the RBPU bit is
cleared. Disabled when analog input is enabled.
A/D Input Channel 12.
Comparator 3 Input D.
External Interrupt 0 input.
Remappable Peripheral Pin 3 input.
PORTB<1> data input; weak pull-up when the RBPU bit is
cleared. Disabled when analog input is enabled.
A/D Input Channel 10.
Comparator 3 Input C.
Parallel Master Port byte enable.
Asynchronous serial transmit data output (USART module).
Remappable Peripheral Pin 4 input.
PORTB<2> data input; weak pull-up when the RBPU bit is
cleared. Disabled when analog input is enabled.
A/D Input Channel 8.
Comparator 2 Input C.
CTMU Edge 1 input.
Parallel Master Port address.
External USB transceiver D- data output.
Remappable Peripheral Pin 5 input.
PORTB<3> data input; weak pull-up when the RBPU bit is
cleared. Disabled when analog input is enabled.
A/D Input Channel 9.
Comparator 3 Input A.
CTMU Edge 2 input.
Parallel Master Port address.
External USB transceiver D+ data output.
Remappable Peripheral Pin 6 input.
LATB<0> data output; not affected by analog input.
Remappable Peripheral Pin 3 output.
LATB<1> data output; not affected by analog input.
Remappable Peripheral Pin 4 output.
LATB<2> data output; not affected by analog input.
Reference output clock.
Remappable Peripheral Pin 5 output.
LATB<3> data output; not affected by analog input.
Remappable Peripheral Pin 6 output.
PIC18F47J53 FAMILY
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Description
DS39964B-page 149
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