PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 213

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.4
Timer1 can be configured for 16-bit reads and writes.
When the RD16 control bit (T1CON<1>) is set, the
address for TMR1H is mapped to a buffer register for
the high byte of Timer1. A read from TMR1L loads the
contents of the high byte of Timer1 into the Timer1 High
Byte Buffer register. This provides the user with the
ability to accurately read all 16 bits of Timer1 without
having to determine whether a read of the high byte,
followed by a read of the low byte, has become invalid
due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
13.5
An on-chip crystal oscillator circuit is incorporated
between pins, T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a
low-power circuit rated for 32 kHz crystals. It will
continue to run during all power-managed modes. The
circuit for a typical LP oscillator is depicted in
Figure 13-2. Table 13-2 provides the capacitor selection
for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 13-2:
 2010 Microchip Technology Inc.
Note:
Timer1 16-Bit Read/Write Mode
Timer1 Oscillator
12 pF
12 pF
C1
C2
See the Notes with Table 13-2 for additional
information about capacitor selection.
32.768 kHz
XTAL
EXTERNAL COMPONENTS
FOR THE TIMER1 LP
OSCILLATOR
T1OSI
T1OSO
PIC18F47J53
Preliminary
PIC18F47J53 FAMILY
TABLE 13-2:
The Timer1 crystal oscillator drive level is determined
based on the SOSCSEL (CONFIG2L<4:3>) Configura-
tion
(SOSCSEL<1:0> = 11) is intended to drive a wide vari-
ety of 32.768 kHz crystals with a variety of load capac-
itance (C
The Lower Drive Level mode is highly optimized for
extremely low-power consumption. It is not intended to
drive all types of 32.768 kHz crystals. In the Low Drive
Level mode, the crystal oscillator circuit may not work
correctly if excessively large discrete capacitors are
placed on the T1OSI and T1OSO pins. This mode is
only designed to work with discrete capacitances of
approximately 3 pF-10 pF on each pin.
Crystal manufacturers usually specify a C
capacitance) rating for their crystals. This value is
related to, but not necessarily the same as, the values
that should be used for C1 and C2 in Figure 13-2. See
the crystal manufacturer’s applications information for
more details on how to select the optimum C1 and C2
for a given crystal. The optimum value depends in part
on the amount of parasitic capacitance in the circuit,
which is often unknown. Therefore, after values have
been selected, it is highly recommended that thorough
testing and validation of the oscillator be performed.
Oscillator
Note 1: Microchip suggests these values as a
Type
LP
bits.
2: Higher capacitance increases the stability
3: Since each resonator/crystal has its own
4: Capacitor values are for design guidance
5: Incorrect capacitance value may result in
L
) ratings.
starting point in validating the oscillator
circuit.
of the oscillator but also increases the
start-up time.
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
components.
only. Values listed would be typical of a
C
SOSCSEL<1:0> = 11.
a frequency not meeting the crystal
manufacturer’s tolerance specification.
L
The
= 10
32 kHz
Freq.
CAPACITOR SELECTION FOR
THE TIMER
OSCILLATOR
Higher
pF
values
rated
12 pF
Drive
C1
(2,3,4,5)
DS39964B-page 213
(1)
crystal
of
Level
12 pF
external
C2
L
when
mode
(1)
(load