PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 358

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J53 FAMILY
FIGURE 21-7:
TABLE 21-6:
21.2.4
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the BRG is inactive and a
proper byte reception cannot be performed. The
auto-wake-up feature allows the controller to wake-up
due to activity on the RXx/DTx line while the EUSART
is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCONx<1>). Once set, the typical
receive sequence on RXx/DTx is disabled and the
EUSART remains in an Idle state, monitoring for a
DS39964B-page 358
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
RCREGx
TXSTAx
BAUDCONx
SPBRGHx
SPBRGx
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1:
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after
Name
RXx (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
the third word causing the OERR (Overrun) bit to be set.
These bits are only available on 44-pin devices.
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
EUSARTx Receive Register
EUSARTx Baud Rate Generator High Byte
EUSARTx Baud Rate Generator Low Byte
GIE/GIEH
PMPIF
PMPIE
PMPIP
ABDOVF
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
SSP2IF
SSP2IE
SSP2IP
CSRC
SPEN
Bit 7
ASYNCHRONOUS RECEPTION
Start
bit
(1)
(1)
(1)
bit 0
PEIE/GIEL
BCL2IE
BCL2IP
BCL2IF
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 1
TMR0IE
RXDTP
RC1IE
RC1IP
RC2IE
RC2IP
RC1IF
RC2IF
SREN
TXEN
bit 7/8
Bit 5
Preliminary
Stop
bit
Word 1
RCREGx
TXCKP
Start
INT0IE
TX1IE
TX1IP
TX2IE
TX2IP
CREN
SYNC
TX1IF
TX2IF
bit
Bit 4
bit 0
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on
the RXx/DTx line. (This coincides with the start of a
Sync Break or a Wake-up Signal character for the
LIN/J2602 protocol.)
Following a wake-up event, the module generates an
RCxIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 21-8) and asynchronously if the device is in
Sleep mode (Figure 21-9). The interrupt condition is
cleared by reading the RCREGx register.
TMR4IE
TMR4IP
TMR4IF
ADDEN
SSP1IF
SSP1IE
SSP1IP
SENDB
BRG16
RBIE
Bit 3
bit 7/8
Word 2
RCREGx
Stop
CTMUIF
CTMUIE
CTMUIP
TMR0IF
CCP1IE
CCP1IP
CCP1IF
bit
BRGH
FERR
Bit 2
—
Start
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bit
TMR3GIF
TMR3GIE
TMR3GIP
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
WUE
Bit 1
bit 7/8
Stop
bit
TMR1IE
TMR1IP
TMR1IF
RTCCIF
RTCCIE
RTCCIP
ABDEN
RX9D
TX9D
Bit 0
RBIF