PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 396

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J53 FAMILY
23.5.1.1
The ACTVIF bit cannot be cleared immediately after
the USB module wakes up from Suspend mode or
while the USB module is suspended. A few clock
cycles are required to synchronize the internal hard-
ware state machine before the ACTVIF bit can be
cleared by firmware. Clearing the ACTVIF bit before
the internal hardware is synchronized may not have an
effect on the value of ACTVIF. Additionally, if the USB
module uses the clock from the 96 MHz PLL source,
then after clearing the SUSPND bit, the USB module
EXAMPLE 23-1:
DS39964B-page 396
Assembly:
LOOP:
DONE:
C:
UCONbits.SUSPND = 0;
while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; }
BCF
BTFSS
BRA
BCF
BRA
Bus Activity Detect Interrupt Bit
(ACTVIF)
UCON, SUSPND
UIR, ACTVIF
DONE
UIR, ACTVIF
LOOP
CLEARING ACTVIF BIT (UIR<2>)
Preliminary
may not be immediately operational while waiting for
the 96 MHz PLL to lock. The application code should
clear the ACTVIF flag as provided in Example 23-1.
Note:
Only one ACTVIF interrupt is generated
when resuming from the USB bus Idle con-
dition. If user firmware clears the ACTVIF
bit, the bit will not immediately become set
again, even when there is continuous bus
traffic. Bus traffic must cease long enough
to generate another IDLEIF condition
before another ACTVIF interrupt can be
generated.
 2010 Microchip Technology Inc.