PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 404

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PIC18F27J53T-I/SO

Manufacturer Part Number
PIC18F27J53T-I/SO
Description
28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets

Specifications of PIC18F27J53T-I/SO

Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
PIC18F47J53 FAMILY
23.9
This section presents some of the basic USB concepts
and useful information necessary to design a USB
device. Although much information is provided in this
section, there is a plethora of information provided
within the USB specifications and class specifications.
Thus, the reader is encouraged to refer to the USB
specifications for more information (www.usb.org). If
you are very familiar with the details of USB, then this
section serves as a basic, high-level refresher of USB.
23.9.1
USB device functionality is structured into a layered
framework, graphically illustrated in Figure 23-12.
Each level is associated with a functional level within
the device. The highest layer, other than the device, is
the configuration. A device may have multiple configu-
rations. For example, a particular device may have
multiple power requirements based on Self-Power Only
or Bus Power Only modes.
For each configuration, there may be multiple
interfaces. Each interface could support a particular
mode of that configuration.
Below the interface is the endpoint(s). Data is directly
moved at this level. There can be as many as
16 bidirectional endpoints. Endpoint 0 is always a
control endpoint, and by default, when the device is on
the bus, Endpoint 0 must be available to configure the
device.
FIGURE 23-12:
DS39964B-page 404
Overview of USB
LAYERED FRAMEWORK
Endpoint
USB LAYERS
Endpoint
Interface
Endpoint
Configuration
Preliminary
Device
23.9.2
Information communicated on the bus is grouped into
1 ms time slots, referred to as frames. Each frame can
contain many transactions to various devices and
endpoints. See Figure 23-8 for an example of a
transaction within a frame.
23.9.3
There are four transfer types defined in the USB
specification.
• Isochronous: This type provides a transfer
• Bulk: This type of transfer method allows for large
• Interrupt: This type of transfer provides for
• Control: This type provides for device setup
While full-speed devices support all transfer types,
low-speed devices are limited to interrupt and control
transfers only.
23.9.4
Power is available from the USB. The USB specifica-
tion defines the bus power requirements. Devices may
either be self-powered or bus-powered. Self-powered
devices draw power from an external source, while
bus-powered devices use power supplied from the bus.
Endpoint
method for large amounts of data (up to
1023 bytes) with timely delivery ensured;
however, the data integrity is not ensured. This is
good for streaming applications where small data
loss is not critical, such as audio.
amounts of data to be transferred with ensured
data integrity; however, the delivery timeliness is
not ensured.
ensured timely delivery for small blocks of data,
plus data integrity is ensured.
control.
To Other Configurations (if any)
Interface
FRAMES
TRANSFERS
POWER
Endpoint
To Other Interfaces (if any)
 2010 Microchip Technology Inc.

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