PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 317

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.5.3.4
Unlike 5-Bit Address Masking mode, 7-Bit Address
Masking mode uses a mask of up to eight bits (in 10-bit
addressing) to define a range of addresses than can be
Acknowledged, using the lowest bits of the incoming
address. This allows the module to Acknowledge up to
127 different addresses with 7-bit addressing, or
255 with 10-bit addressing (see Example 20-4). This
mode is the default configuration of the module and is
selected when MSSPMSK is unprogrammed (‘1’).
The address mask for 7-Bit Address Masking mode is
stored in the SSPxMSK register, instead of the
SSPxCON2 register. SSPxMSK is a separate, hard-
ware register within the module, but it is not directly
addressable. Instead, it shares an address in the SFR
space with the SSPxADD register. To access the
SSPxMSK register, it is necessary to select MSSP
mode, ‘1001’ (SSPCON1<3:0> = 1001), and then read
or write to the location of SSPxADD.
To use 7-Bit Address Masking mode, it is necessary to
initialize SSPxMSK with a value before selecting the
I
sequence of events is:
1.
2.
3.
EXAMPLE 20-4:
 2010 Microchip Technology Inc.
2
C Slave Addressing mode. Thus, the required
7-Bit Addressing:
10-Bit Addressing:
Select
(SSPxCON2<3:0> = 1001).
Write the mask value to the appropriate
SSPxADD register address (FC8h for MSSP1,
F6Eh for MSSP2).
Set
(SSPxCON2<3:0> = 0111 for 10-bit addressing,
0110 for 7-bit addressing).
SSPxADD<7:1>= 1010 000
SSPxMSK<7:1>= 1111 001
Addresses Acknowledged = A8h, A6h, A4h, A0h
SSPxADD<7:0> = 1010 0000 (the two MSbs are ignored in this example since they are not affected)
SSPxMSK<5:1> = 1111 0
Addresses Acknowledged = A8h, A6h, A4h, A0h
the
7-Bit Address Masking Mode
SSPxMSK
appropriate
ADDRESS MASKING EXAMPLES IN 7-BIT MASKING MODE
I
2
Access
C
Slave
mode
mode
Preliminary
PIC18F47J53 FAMILY
Setting or clearing mask bits in SSPxMSK behaves in
the opposite manner of the ADMSK bits in 5-Bit
Address Masking mode. That is, clearing a bit in
SSPxMSK causes the corresponding address bit to be
masked; setting the bit requires a match in that
position. SSPxMSK resets to all ‘1’s upon any Reset
condition, and therefore, has no effect on the standard
MSSP operation until written with a mask value.
With
SSPxMSK<7:1> bits mask the corresponding address
bits in the SSPxADD register. For any SSPxMSK bits
that are active (SSPxMSK<n> = 0), the corresponding
SSPxADD address bit is ignored (SSPxADD<n> = x).
For the module to issue an address Acknowledge, it is
sufficient to match only on addresses that do not have
an active address mask.
With 10-Bit Address Masking mode, SSPxMSK<7:0>
bits mask the corresponding address bits in the
SSPxADD register. For any SSPxMSK bits that are
active (= 0), the corresponding SSPxADD address bit
is ignored (SSPxADD<n> = x).
Note:
7-Bit
The two MSbs of the address are not
affected by address masking.
Address
Masking
DS39964B-page 317
mode,
the