PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 345

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.0
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is one of two
serial I/O modules. (Generically, the EUSART is also
known as a Serial Communications Interface or SCI.)
The EUSART can be configured as a full-duplex
asynchronous system that can communicate with
peripheral devices, such as CRT terminals and
personal computers. It can also be configured as a
half-duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs and so on.
The Enhanced USART module implements additional
features, including Automatic Baud Rate Detection and
calibration, automatic wake-up on Sync Break recep-
tion, and 12-bit Break character transmit. These make
it ideally suited for use in Local Interconnect Network
bus (LIN/J2602 bus) systems.
All members of the PIC18F47J53 family are equipped
with two independent EUSART modules, referred to as
EUSART1 and EUSART2. They can be configured in
the following modes:
• Asynchronous (full-duplex) with:
• Synchronous – Master (half-duplex) with
• Synchronous – Slave (half-duplex) with selectable
 2010 Microchip Technology Inc.
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
selectable clock polarity
clock polarity
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
Preliminary
PIC18F47J53 FAMILY
The pins of EUSART1 and EUSART2 are multiplexed
with the functions of PORTC (RC6/CCP9/TX1/CK1/RP17
and RC7/CCP10/RX1/DT1/SDO1/RP18) and remapped
(RPn1/TX2/CK2 and RPn2/RX2/DT2), respectively. In
order to configure these pins as an EUSART:
• For EUSART1:
• For EUSART2:
The TXx/CKx I/O pins have an optional open-drain
output capability. By default, when this pin is used by
the EUSART as an output, it will function as a standard
push-pull CMOS output. The TXx/CKx I/O pins’
open-drain, output feature can be enabled by setting
the corresponding UxOD bit in the ODCON2 register.
For more details, see Section 20.3.3 “Open-Drain
Output Option”.
The operation of each Enhanced USART module is
controlled through three registers:
• Transmit Status and Control (TXSTAx)
• Receive Status and Control (RCSTAx)
• Baud Rate Control (BAUDCONx)
These are covered in detail in Register 21-1,
Register 21-2 and Register 21-3, respectively.
- SPEN bit (RCSTA1<7>) must be set (= 1)
- TRISC<7> bit must be set (= 1)
- TRISC<6> bit must be cleared (= 0) for
- TRISC<6> bit must be set (= 1) for
- SPEN bit (RCSTA2<7>) must be set (= 1)
- TRIS bit for RPn2/RX2/DT2 = 1
- TRIS bit for RPn1/TX2/CK2 = 0 for
- TRISC<6> bit must be set (= 1) for
Note:
Note:
Asynchronous and Synchronous Master
modes
Synchronous Slave mode
Asynchronous and Synchronous Master
modes
Synchronous Slave mode
The EUSART control will automatically
reconfigure the pin from input to output as
needed.
Throughout this section, references to
register and bit names that may be associ-
ated with a specific EUSART module are
referred to generically by the use of ‘x’ in
place of the specific module number.
Thus, “RCSTAx” might refer to the
Receive
EUSART1 or EUSART2.
Status
register
DS39964B-page 345
for
either