PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 95

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 6-4:
 2010 Microchip Technology Inc.
FDCh
FDBh
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC8h
FC7h
FC6h
FC5h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
FBFh
FBEh
FBDh
FBCh
FBBh
FBAh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
Legend:
Note 1:
Addr.
2:
3:
ECCP1AS
ECCP2AS
CTMUCONL
SPBRG1
PREINC2
PLUSW2
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
CM1CON
CM2CON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON1
SSP1CON2
SSP1CON2
ADRESH
ADRESL
ADCON0
ADCON1
WDTCON
PSTR1CON
ECCP1DEL
CCPR1H
CCPR1L
CCP1CON
PSTR2CON
ECCP2DEL
CCPR2H
CCPR2L
CCP2CON
CTMUCONH
CTMUICON
RCREG1
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Implemented only for 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
Implemented only for 28-pin devices (PIC18F26J53, PIC18F27J53, PIC18LF26J53 and PIC18LF27J53).
Implemented only for devices with 128 Kbyte of program memory (PIC18F27J53, PIC18F47J53, PIC18LF27J53 and PIC18LF47J53).
File Name
REGISTER FILE SUMMARY (PIC18F47J53 FAMILY) (CONTINUED)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
Indirect Data Memory Address Pointer 2 Low Byte
Timer0 Register High Byte
Timer0 Register Low Byte
Timer1 Register High Byte
Timer1 Register Low Bytes
Timer2 Register
Timer2 Period Register
MSSP1 Receive Buffer/Transmit Register
MSSP1 Address Register (I
A/D Result Register High Byte
A/D Result Register Low Byte
ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
EUSART1 Baud Rate Generator Register Low Byte
EUSART1 Receive Register
TMR1CS1
EDG2POL
TMR0ON
CTMUEN
REGSLP
P1RSEN
P2RSEN
VCFG1
CMPL1
CMPL1
ITRIM5
IDLEN
WCOL
GCEN
GCEN
ADFM
MSK7
P1M1
P2M1
CON
CON
IPEN
Bit 7
SMP
—
—
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
EDG2SEL1 EDG2SEL0
TMR1CS0
ACKSTAT
ACKSTAT
LVDSTAT
SSPOV
T08BIT
VCFG0
ADCAL
CMPL0
P1DC6
CMPL0
P2DC6
ITRIM4
IRCF2
MSK6
P1M0
P2M0
Bit 6
COE
COE
CKE
—
—
—
—
2
CTMUSIDL
T1CKPS1
C™ Slave Mode). MSSP1 Baud Rate Reload Register (I
ADMSK5
ULPLVL
SSPEN
ACKDT
ACQT2
P1DC5
DC1B1
P2DC5
DC2B1
ITRIM3
IRCF1
CPOL
CPOL
MSK5
T0CS
CHS3
Bit 5
D/A
CM
—
—
—
—
Preliminary
STRSYNC
STRSYNC
EDG1POL
T1CKPS0
ADMSK4
EVPOL1
EVPOL1
VBGOE
ACKEN
ACQT1
ITRIM2
P1DC4
DC1B0
P2DC4
DC2B0
IRCF0
TGEN
MSK4
CHS2
T0SE
Bit 4
CKP
—
RI
N
P
PIC18F47J53 FAMILY
Indirect Data Memory Address Pointer 2 High Byte
EDG1SEL1 EDG1SEL0
T1OSCEN
PSS1AC1
PSS2AC1
ADMSK3
CCP1M3
CCP2M3
EVPOL0
EVPOL0
EDGEN
SSPM3
ACQT0
ITRIM1
P1DC3
P2DC3
MSK3
RCEN
STRD
STRD
OSTS
CHS1
Bit 3
PSA
OV
TO
DS
S
EDGSEQEN
PSS1AC0
PSS2AC0
TMR2ON
ADMSK2
CCP1M2
CCP2M2
T1SYNC
SSPM2
ADCS2
ULPEN
P1DC2
P2DC2
ITRIM0
T0PS2
CREF
CREF
MSK2
CHS0
STRC
STRC
FLTS
Bit 2
R/W
PEN
PD
Z
EDG2STAT
GO/DONE
T2CKPS1
2
PSS1BD1
PSS2BD1
ULPSINK
ADMSK1
CCP1M1
CCP2M1
IDISSEN
C Master Mode).
SSPM1
ADCS1
P1DC1
P2DC1
T0PS1
IRNG1
CCH1
CCH1
MSK1
RSEN
STRB
STRB
SCS1
RD16
Bit 1
POR
DC
UA
EDG1STAT 0000 00xx
PSS1BD0
PSS2BD0
T2CKPS0
SWDTEN
TMR1ON
CCP1M0
CCP2M0
CTTRIG
SSPM0
ADCS0
P1DC0
P2DC0
T0PS0
IRNG0
DS39964B-page 95
CCH0
CCH0
ADON
SCS0
MSK0
STRA
STRA
Bit 0
BOR
SEN
SEN
BF
C
---- xxxx
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
0110 q000
0001 1111
0001 1111
0-11 11qq
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
---- ----
1111 1111
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1xx0 0000
00-0 0001
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
00-0 0001
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0-00 0000
0000 0000
0000 0000
0000 0000
POR, BOR
Value on
N/A
N/A