PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 92

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J53 FAMILY
6.3.5
The SFRs are registers used by the CPU and periph-
eral modules for controlling the desired operation of the
device. These registers are implemented as static
RAM. SFRs start at the top of data memory (FFFh) and
extend downward to occupy more than the top half of
Bank 15 (F40h to FFFh). Table 6-2, Table 6-3 and
Table 6-4 provide a list of these registers.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their corresponding chapters, while the
TABLE 6-2:
DS39964B-page 92
Note 1:
Address
FFDh
FFCh
FEEh
FEDh
FECh
FEBh
FEAh
FFEh
FFBh
FEFh
FFFh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FE9h
FE8h
FE7h
FE6h
FE5h
FE4h
FE3h
FE2h
FE1h
FE0h
2:
3:
4:
5:
POSTDEC0
POSTDEC1
T
This register is not available on 28-pin devices.
SSPxADD and SSPxMSK share the same address.
PMADDRH and PMDOUTH share the same address and PMADDRL and PMDOUTL share the same address.
PMADDRx is used in Master modes and PMDOUTx is used in Slave modes.
Reserved: Do not write to this location.
POSTINC0
POSTINC1
SPECIAL FUNCTION REGISTERS
PREINC0
PREINC1
PLUSW0
PLUSW1
h
TBLPTRU
TBLPTRH
INTCON3
TBLPTRL
INTCON2
STKPTR
PCLATH
PCLATU
INTCON
INDF0
INDF1
TABLAT
PRODH
is is not a physical register.
PRODL
FSR0H
FSR1H
Name
FSR0L
WREG
FSR1L
TOSU
TOSH
TOSL
BSR
PCL
ACCESS BANK SPECIAL FUNCTION REGISTER MAP
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Address
FDEh
FDDh
FDCh
FDBh
FDAh
FCEh
FCDh
FCCh
FCBh
FCAh
FDFh
FCFh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
POSTDEC2
POSTINC2
SSP1ADD
PREINC2
SSP1CON1
SSP1CON2
PLUSW2
SSP1STAT
SSP1BUF
OSCCON
WDTCON
CM1CON
CM2CON
ADRESH
ADCON0
ADCON1
INDF2
ADRESL
STATUS
TMR0H
T0CON
TMR1H
T1CON
T2CON
FSR2H
TMR0L
TMR1L
Name
FSR2L
RCON
TMR2
—
PR2
(5)
(1)
(1)
(1)
(3)
(1)
(1)
Address
Preliminary
FBEh
FBDh
FBCh
FBBh
FBAh
FADh
FACh
FBFh
FB9h
FB5h
FAEh
FABh
FAAh
FB8h
FB7h
FB6h
FB4h
FB3h CTMUCONH
FB2h CTMUCONL
FB1h
FB0h
FAFh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
PSTR1CON
PSTR2CON
ECCP1DEL
ECCP2DEL
CTMUICON
CCP1CON
CCP2CON
ECCP1AS
ECCP2AS
RCREG1
RCREG2
CCPR1H
CCPR2H
SPBRG1
TXREG1
SPBRG2
TXREG2
EECON2
EECON1
CCPR1L
CCPR2L
RCSTA1
TXSTA1
TXSTA2
Name
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
ALU’s STATUS register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s
Note:
Address
F9Dh
F9Ch
F8Dh
F8Ch
The SFRs located between EB0h and
F5Fh are not part of the Access Bank.
Either BANKED instructions (using BSR) or
the MOVFF instruction should be used to
access these locations. When program-
ming in MPLAB
automatically
addressing mode.
F9Eh
F9Bh
F9Ah
F8Eh
F8Bh
F8Ah
F9Fh
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
OSCCON2
OSCTUNE
DMACON1
DMACON2
HLVDCON
PORTE
PORTD
T3GCON
T1GCON
RCSTA2
LATD
PORTC
LATE
PORTB
PORTA
Name
TRISE
TRISD
TRISC
TRISA
TRISB
LATC
LATB
LATA
IPR1
PIR1
PIE1
IPR5
PIR5
PIE5
IPR4
PIR4
PIE4
 2010 Microchip Technology Inc.
(2)
(2)
(2)
(2)
(5)
®
use
Address
C18, the compiler will
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F7Fh
F79h
F6Fh
F66h
F65h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F69h
F68h
F67h
F64h
F63h
F62h
F61h
F60h
the
PMADDRH
PMADDRL
SSP2ADD
BAUDCON1
BAUDCON2
PMDIN1H
appropriate
SSP2CON1
SSP2CON2
PMDIN1L
SSP2STAT
RXADDRH
SPBRGH1
SPBRGH2
TXADDRH
RXADDRL
SSP2BUF
TXADDRL
DMABCH
DMABCL
CMSTAT
UFRMH
TMR3H
T3CON
T4CON
UFRML
TMR3L
Name
USTAT
UCON
TMR4
UEIR
PR4
UIR
(2,4)
(2,4)
(2)
(2)
(3)