PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 384

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J53 FAMILY
23.2.2.2
The PIC18F47J53 family devices have built-in pull-up
resistors designed to meet the requirements for
low-speed and full-speed USB. The UPUEN bit
(UCFG<4>) enables the internal pull-ups. Figure 23-1
shows the pull-ups and their control.
23.2.2.3
External pull-ups may also be used. The V
be used to pull up D+ or D-. The pull-up resistor must be
1.5 k (±5%) as required by the USB specifications.
Figure 23-2 provides an example of external circuitry.
FIGURE 23-2:
DS39964B-page 384
Note:
Note:
PIC
The above setting shows a typical connection
for a full-speed configuration using an on-chip
regulator and an external pull-up resistor.
®
A compliant USB device should never
source any current onto the +5V V
of the USB cable. Additionally, USB
devices should not source any current on
the D+ and D- data lines whenever the
+5V V
to be USB compliant, applications which
are not purely bus-powered should moni-
tor the V
USB module and the D+ or D- pull-up
resistor until V
V
by a 5V tolerant I/O pin, or if a resistive
divider is used, by an analog capable pin.
MCU
BUS
Internal Pull-up Resistors
External Pull-up Resistors
V
USB
D+
D-
can be connected to and monitored
BUS
BUS
line is less than 1.17V. In order
EXTERNAL CIRCUITRY
line, and avoid turning on the
1.5 k
BUS
is greater than 1.17V.
Controller/HUB
Host
USB
BUS
pin may
line
Preliminary
23.2.2.4
The usage of ping-pong buffers is configured using the
PPB<1:0> bits. Refer to Section 23.4.4 “Ping-Pong
Buffering” for a complete explanation of the ping-pong
buffers.
23.2.2.5
An automatic eye pattern test can be generated by the
module when the UCFG<7> bit is set. The eye pattern
output will be observable based on module settings,
meaning that the user is first responsible for configuring
the SIE clock settings, pull-up resistor and Transceiver
mode. In addition, the module has to be enabled.
Once UTEYE is set, the module emulates a switch from
a receive to transmit state and will start transmitting a
J-K-J-K bit sequence (K-J-K-J for full speed). The
sequence will be repeated indefinitely while the Eye
Pattern Test mode is enabled.
Note that this bit should never be set while the module
is connected to an actual USB system. This Test mode
is intended for board verification to aid with USB certi-
fication tests. It is intended to show a system developer
the noise integrity of the USB signals which can be
affected by board traces, impedance mismatches and
proximity to other system components. It does not
properly test the transition from a receive to a transmit
state. Although the eye pattern is not meant to replace
the more complex USB certification test, it should aid
during first order system debugging.
Ping-Pong Buffer Configuration
Eye Pattern Test Enable
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