PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 251

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 17-2:
17.2.4
Since the year range on the RTCC module is 2000 to
2099, the leap year calculation is determined by any
year divisible by ‘4’ in the above range. Only February
is effected in a leap year.
February will have 29 days in a leap year and 28 days in
any other year.
17.2.5
All Timer registers containing a time value of seconds or
greater are writable. The user configures the time by
writing the required year, month, day, hour, minutes and
seconds to the Timer registers, via register pointers (see
Section 17.2.8 “Register Mapping”).
The timer uses the newly written values and proceeds
with the count from the required starting point.
The RTCC is enabled by setting the RTCEN bit
(RTCCFG<7>). If enabled, while adjusting these
registers, the timer still continues to increment. However,
any time the MINSEC register is written to, both of the
timer prescalers are reset to ‘0’. This allows fraction of a
second synchronization.
The Timer registers are updated in the same cycle as
the write instruction’s execution by the CPU. The user
must ensure that when RTCEN = 1, the updated
registers will not be incremented at the same time. This
can be accomplished in several ways:
• By checking the RTCSYNC bit (RTCCFG<4>)
• By checking the preceding digits from which a
• By updating the registers immediately following
The user has visibility to the half-second field of the
counter. This value is read-only and can be reset only
by writing to the lower half of the SECONDS register.
 2010 Microchip Technology Inc.
Note 1:
carry can occur
the seconds pulse (or alarm interrupt)
09 (September)
11 (November)
12 (December)
02 (February)
01 (January)
10 (October)
08 (August)
03 (March)
06 (June)
04 (April)
05 (May)
07 (July)
Month
See Section 17.2.4 “Leap Year”.
LEAP YEAR
GENERAL FUNCTIONALITY
DAY TO MONTH ROLLOVER
SCHEDULE
Maximum Day Field
28 or 29
31
31
30
31
30
31
31
30
31
30
31
(1)
Preliminary
PIC18F47J53 FAMILY
17.2.6
The RTCSYNC bit indicates a time window during
which the RTCC Clock Domain registers can be safely
read and written without concern about a rollover.
When RTCSYNC = 0, the registers can be safely
accessed by the CPU.
Whether RTCSYNC = 1 or 0, the user should employ a
firmware solution to ensure that the data read did not
fall on a rollover boundary, resulting in an invalid or
partial read. This firmware solution would consist of
reading each register twice and then comparing the two
values. If the two values matched, then, a rollover did
not occur.
17.2.7
In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RTCCFG<5>) must be
set.
To avoid accidental writes to the RTCC Timer register,
it
(RTCCFG<5>) be kept clear at any time other than
while writing to it. For the RTCWREN bit to be set, there
is only one instruction cycle time window allowed
between the 55h/AA sequence and the setting of
RTCWREN. For that reason, it is recommended that
users follow the code example in Example 17-1.
EXAMPLE 17-1:
17.2.8
To limit the register interface, the RTCC Timer and
Alarm
corresponding register pointers. The RTCC Value reg-
ister window (RTCVALH<15:8> and RTCVALL<7:0>)
uses the RTCPTR bits (RTCCFG<1:0>) to select the
required Timer register pair.
By reading or writing to the RTCVALH register, the
RTCC Pointer value (RTCPTR<1:0>) decrements by 1
until it reaches ‘00’. Once it reaches ‘00’, the MINUTES
and SECONDS value will be accessible through
RTCVALH and RTCVALL until the pointer value is
manually changed.
movlb
bcf
movlw
movwf
movlw
movwf
bsf
is
recommended
Timer
SAFETY WINDOW FOR REGISTER
READS AND WRITES
WRITE LOCK
REGISTER MAPPING
0x0F
INTCON, GIE
0x55
EECON2
0xAA
EECON2
RTCCFG,RTCWREN
registers
SETTING THE RTCWREN
BIT
that
are
;RTCCFG is banked
;Disable interrupts
the
accessed
DS39964B-page 251
RTCWREN
through
bit