PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 365

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.4
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTAx<7>). This mode differs from the
Synchronous Master mode in that the shift clock is sup-
plied externally at the CKx pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
21.4.1
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
If two words are written to the TXREGx, and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
TABLE 21-9:
 2010 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
TXREGx
TXSTAx
BAUDCONx
SPBRGHx
SPBRGx
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1:
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in the TXREGx
register.
Flag bit, TXxIF, will not be set.
When the first word has been shifted out of TSR,
the TXREGx register will transfer the second word
to the TSR and flag bit, TXxIF, will now be set.
Name
EUSART Synchronous Slave
Mode
These pins are only available on 44-pin devices.
EUSART SYNCHRONOUS SLAVE
TRANSMISSION
EUSARTx Transmit Register
EUSARTx Baud Rate Generator High Byte
EUSARTx Baud Rate Generator Low Byte
GIE/GIEH
PMPIF
PMPIE
PMPIP
ABDOVF
SSP2IE
SSP2IP
SSP2IF
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
CSRC
SPEN
Bit 7
(1)
(1)
(1)
PEIE/GIEL
BCL2IF
BCL2IE
BCL2IP
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
TMR0IE
RXDTP
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
TXEN
Bit 5
Preliminary
TXCKP
INT0IE
TX1IE
TX1IP
TX2IE
TX2IP
CREN
SYNC
TX1IF
TX2IF
Bit 4
PIC18F47J53 FAMILY
e)
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
If enable bit, TXxIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Clear bits, CREN and SREN.
If interrupts are desired, set enable bit, TXxIE.
If 9-bit transmission is desired, set bit, TX9.
Enable the transmission by setting enable bit,
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Start transmission by loading data to the
TXREGx register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR4IF
TMR4IE
TMR4IP
SSP1IF
SSP1IE
SSP1IP
ADDEN
SENDB
BRG16
RBIE
Bit 3
CTMUIF
CTMUIE
CTMUIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
—
TMR3GIE
TMR3GIP
TMR3GIF
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
WUE
Bit 1
DS39964B-page 365
TMR1IE
TMR1IP
RTCCIF
RTCCIE
RTCCIP
TMR1IF
ABDEN
RX9D
TX9D
Bit 0
RBIF