PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 454

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PIC18F27J53T-I/SO

Manufacturer Part Number
PIC18F27J53T-I/SO
Description
28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets

Specifications of PIC18F27J53T-I/SO

Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
PIC18F47J53 FAMILY
FIGURE 28-2:
DS39964B-page 454
OR
PIC18LFXXJ53 Devices (Regulator Disabled):
PIC18FXXJ53 Devices (Regulator Enabled):
2.5V
C
F
3.3V
2.5V
3.3V
CONNECTIONS FOR THE
ON-CHIP REGULATOR
V
V
V
V
V
V
V
V
V
DD
DDCORE
SS
DD
DDCORE
SS
DD
DDCORE
SS
PIC18LFXXJ53
PIC18LFXXJ53
PIC18FXXJ53
/V
/V
/V
CAP
CAP
CAP
Preliminary
28.3.2
When the on-chip regulator is enabled, PIC18F47J53
family devices also have a simple brown-out capability.
If the voltage supplied to the regulator is inadequate to
maintain a minimum output level, the regulator Reset
circuitry will generate a Brown-out Reset (BOR). This
event is captured by the BOR flag bit (RCON<0>).
The operation of the BOR is described in more detail in
Section 5.4
Section 5.4.1 “Detecting BOR”. The brown-out voltage
levels are specific in Section 31.1 “DC Characteristics:
Supply Voltage PIC18F47J53 Family (Industrial)”.
28.3.3
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, V
exceed V
28.3.4
When enabled, the on-chip regulator always consumes
a small incremental amount of current over I
includes when the device is in Sleep mode, even
though the core digital logic does not require much
power. To provide additional savings in applications
where power resources are critical, the regulator can
be configured to automatically enter a lower quiescent
draw Standby mode whenever the device goes into
Sleep mode. This feature is controlled by the REGSLP
bit (WDTCON<7>, Register 28-11). If this bit is set
upon entry into Sleep mode, the regulator will transition
into a lower power state. In this state, the regulator still
provides a regulated output voltage necessary to
maintain SRAM state information, but consumes less
quiescent current.
Substantial Sleep mode power savings can be
obtained by setting the REGSLP bit, but device
wake-up time will increase in order to insure the
regulator has enough time to stabilize.
DD
ON-CHIP REGULATOR AND BOR
POWER-UP REQUIREMENTS
OPERATION IN SLEEP MODE
by 0.3 volts.
“Brown-out
 2010 Microchip Technology Inc.
Reset
DDCORE
(BOR)”
should not
DD
. This
and

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