PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 344

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J53 FAMILY
TABLE 20-4:
DS39964B-page 344
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PIR3
PIE3
IPR3
TRISC
TRISB
SSP1BUF
SSP1ADD
SSPxMSK
SSPxCON1
SSPxCON2
SSPxSTAT
SSP2BUF
SSP2ADD
Legend:
Note 1:
Name
2:
3:
(1)
— = unimplemented, read as ‘0’. Shaded cells are not used by the MSSPx module in I
SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I
mode operations in 7-Bit Masking mode. See Section 20.5.3.4 “7-Bit Address Masking Mode” for more
details.
Alternate bit definitions for use in I
These bits are only available on 44-pin devices.
MSSP1 Receive Buffer/Transmit Register
MSSP1 Address Register (I
MSSP2 Receive Buffer/Transmit Register
MSSP2 Address Register (I
GIE/GIEH
PMPIF
PMPIE
PMPIP
OSCFIF
OSCFIE
OSCFIP
TRISC7
SSP2IF
SSP2IE
SSP2IP
TRISB7
WCOL
GCEN
GCEN
REGISTERS ASSOCIATED WITH I
MSK7
Bit 7
SMP
(3)
(3)
(3)
PEIE/GIEL
ACKSTAT
ACKSTAT
TRISC6
TRISB6
BCL2IF
BCL2IE
BCL2IP
SSPOV
CM2IE
CM2IP
CM2IF
MSK6
ADIF
ADIE
ADIP
Bit 6
CKE
2
2
C™ Slave mode), MSSP1 Baud Rate Reload Register (I
ADMSK5
C Slave mode), MSSP2 Baud Rate Reload Register (I
TMR0IE
TRISB5
SSPEN
ACKDT
2
CM1IF
CM1IE
CM1IP
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
MSK5
C Slave mode operations only.
Bit 5
D/A
—
(2)
Preliminary
ADMSK4
TRISB4
ACKEN
INT0IE
USBIF
USBIE
USBIP
TX1IE
TX1IP
TX2IE
TX2IP
TX1IF
TX2IF
MSK4
Bit 4
CKP
2
—
P
C™ OPERATION
(2)
ADMSK3
TMR4IE
TMR4IP
TMR4IF
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
TRISB3
SSPM3
RCEN
MSK3
RBIE
Bit 3
—
S
(2)
ADMSK2
CTMUIE
CTMUIP
CTMUIF
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISC2
HLVDIF
HLVDIE
HLVDIP
TRISB2
SSPM2
MSK2
Bit 2
PEN
R/W
 2010 Microchip Technology Inc.
(2)
2
2
ADMSK1
2
TMR3GIE
TMR3GIP
TMR3GIF
C™ mode.
C Master mode)
C Master mode)
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TRISC1
TRISB1
SSPM1
INT0IF
RSEN
MSK1
Bit 1
UA
(2)
2
C Slave
TMR1IF
TMR1IE
TMR1IP
CCP2IE
CCP2IP
RTCCIF
RTCCIE
RTCCIP
CCP2IF
TRISC0
TRISB0
SSPM0
MSK0
RBIF
Bit 0
SEN
SEN
BF