PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 581

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

 2010 Microchip Technology Inc.
I
ADMSK = 01001) ...................................................... 322
I
I
I
I
I
I
I
I
I
Low-Voltage Detect (VDIRMAG = 0) ........................ 422
MSSPx I
MSSPx I
Parallel Master Port Read......................................... 540
Parallel Master Port Write ......................................... 541
Parallel Slave Port Read................................... 189, 191
Parallel Slave Port Write ................................... 189, 192
PWM Auto-Shutdown with Auto-Restart Enabled..... 284
PWM Auto-Shutdown with Firmware Restart............ 284
PWM Direction Change ............................................ 281
PWM Direction Change at Near 100%
Duty Cycle................................................................. 282
PWM Output ............................................................. 266
PWM Output (Active-High)........................................ 276
PWM Output (Active-Low) ........................................ 277
Read and Write, 8-Bit Data, Demultiplexed
Read, 16-Bit Data, Demultiplexed Address .............. 199
Read, 16-Bit Multiplexed Data, Fully Multiplexed
Read, 16-Bit Multiplexed Data, Partially
Read, 8-Bit Data, Fully Multiplexed
Read, 8-Bit Data, Partially Multiplexed Address ....... 196
Read, 8-Bit Data, Partially Multiplexed Address,
Read, 8-Bit Data, Wait States Enabled, Partially
Multiplexed Address.................................................. 196
Repeated Start Condition.......................................... 334
Reset, Watchdog Timer (WDT), Oscillator
Send Break Character Sequence ............................. 360
Slave Synchronization .............................................. 298
Slow Rise Time (MCLR Tied to V
Rise > T
SPI Mode (Master Mode).......................................... 297
SPI Mode (Slave Mode, CKE = 0) ............................ 299
SPI Mode (Slave Mode, CKE = 1) ............................ 299
Steering Event at Beginning of Instruction
Steering Event at End of Instruction
(STRSYNC = 0) ........................................................ 288
Synchronous Reception (Master Mode, SREN) ....... 363
Synchronous Transmission....................................... 361
Synchronous Transmission (Through TXEN) ........... 362
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Not Tied to V
2
2
2
2
2
2
2
2
2
2
C Slave Mode (10-Bit Reception, SEN = 0,
C Slave Mode (10-Bit Reception, SEN = 0) ........... 323
C Slave Mode (10-Bit Reception, SEN = 1) ........... 328
C Slave Mode (10-Bit Transmission)...................... 324
C Slave Mode (7-Bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 0) ............. 319
C Slave Mode (7-Bit Reception, SEN = 1) ............. 327
C Slave Mode (7-Bit Transmission)........................ 321
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ......... 338
ADMSK = 01011).............................................. 320
Sequence (7 or 10-Bit Addressing Mode)......... 329
Address............................................................. 196
16-Bit Address .................................................. 200
Multiplexed Address ......................................... 199
16-Bit Address .................................................. 198
Enable Strobe ................................................... 197
Start-up Timer (OST) and Power-up
Timer (PWRT)................................................... 537
(STRSYNC = 1) ................................................ 288
Not Tied to V
PWRT
2
2
C Bus Data ................................................ 548
C Bus Start/Stop Bits................................. 548
DD
)............................................................. 69
), Case 2 ............................................ 69
DD
), Case 1 .................................... 69
DD
, V
DD
Preliminary
PIC18F47J53 FAMILY
Timing Diagrams and Specifications
Time-out Sequence on Power-up (MCLR
Timer Pulse Generation............................................ 254
Timer0 and Timer1 External Clock ........................... 538
Timer1 Gate Count Enable Mode............................. 215
Timer1 Gate Single Pulse Mode............................... 217
Timer1 Gate Single Pulse/Toggle
Timer1 Gate Toggle Mode........................................ 216
Timer3 Gate Count Enable Mode............................. 226
Timer3 Gate Single Pulse Mode............................... 228
Timer3 Gate Single Pulse/Toggle
Combined Mode ....................................................... 229
Timer3 Gate Toggle Mode........................................ 227
Transition for Entry to Idle Mode ................................ 53
Transition for Entry to SEC_RUN Mode ..................... 49
Transition for Entry to Sleep Mode ............................. 51
Transition for Two-Speed Start-up
Transition for Wake From Idle to Run Mode............... 53
Transition for Wake From Sleep (HSPLL) .................. 51
Transition From RC_RUN Mode to
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL) ........................................... 49
Transition to RC_RUN Mode...................................... 50
USB Signal ............................................................... 553
Write, 16-Bit Data, Demultiplexed Address .............. 199
Write, 16-Bit Multiplexed Data, Fully
Write, 16-Bit Multiplexed Data, Partially
Write, 8-Bit Data, Fully Multiplexed
Write, 8-Bit Data, Partially Multiplexed Address ....... 197
Write, 8-Bit Data, Partially Multiplexed Address,
Write, 8-Bit Data, Wait States Enabled,
AC Characteristics
CLKO and I/O Requirements.................................... 536
Enhanced Capture/Compare/PWM
EUSARTx Synchronous Receive Requirements...... 550
EUSARTx Synchronous Transmission
Requirements ........................................................... 550
Example SPI Mode Requirements (Master Mode,
Example SPI Mode Requirements (Master Mode,
Example SPI Mode Requirements (Slave Mode,
Example SPI Slave Mode Requirements
(CKE = 1).................................................................. 545
External Clock Requirements ................................... 535
I
I
MSSPx I
MSSPx I
Parallel Master Port Read Requirements ................. 541
Parallel Master Port Write Requirements ................. 541
PLL Clock ................................................................. 535
2
2
C Bus Data Requirements (Slave Mode) ............... 547
C Bus Start/Stop Bits Requirements
Tied to V
Combined Mode ............................................... 218
(INTRC to HSPLL)............................................ 455
PRI_RUN Mode.................................................. 50
Multiplexed 16-Bit Address............................... 200
Multiplexed Address ......................................... 200
16-Bit Address .................................................. 198
Enable Strobe................................................... 198
Partially Multiplexed Address ........................... 197
Internal RC Accuracy........................................ 535
Requirements ................................................... 540
CKE = 0)........................................................... 542
CKE = 1)........................................................... 543
CKE = 0)........................................................... 544
(Slave Mode) .................................................... 546
2
2
C Bus Data Requirements ........................ 549
C Bus Start/Stop Bits Requirements......... 548
DD
, V
DD
Rise < T
PWRT
DS39964B-page 581
) ........................ 68