PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 48

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J53 FAMILY
TABLE 4-1:
4.1.3
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Two bits indicate the current clock source and its
status:
(OSCCON2<6>). In general, only one of these bits will
be set in a given power-managed mode. When the
OSTS bit is set, the primary clock would be providing
the device clock. When the SOSCRUN bit is set, the
Timer1 oscillator would be providing the clock. If neither
of these bits is set, INTRC would be clocking the
device.
DS39964B-page 48
Sleep
Deep
Sleep
PRI_RUN
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
Note 1:
Note:
Mode
(3)
2:
3:
OSTS
IDLEN and DSEN reflect their values when the SLEEP instruction is executed.
Deep Sleep turns off the internal core voltage regulator to power down core logic. See Section 4.6 “Deep Sleep
Mode” for more information.
Deep Sleep mode is only available on “F” devices, not “LF” devices.
CLOCK TRANSITIONS AND STATUS
INDICATORS
Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep or Deep
Sleep mode, or one of the Idle modes,
depending on the setting of the IDLEN bit.
DSCONH<7>
DSEN
0
1
0
0
0
0
0
0
LOW-POWER MODES
(OSCCON<3>)
(1)
IDLEN
OSCCON<7,1:0>
N/A
N/A
N/A
0
0
1
1
1
(1)
SCS<1:0>
and
N/A
N/A
00
01
11
00
01
11
SOSCRUN
Powered
Clocked
Clocked
Clocked
CPU
off
Module Clocking
Off
Off
Off
Off
Preliminary
(2)
Powered off RTCC can run uninterrupted using the Timer1 or
Peripherals
Clocked
Clocked
Clocked
Clocked
Clocked
Clocked
Off
4.1.4
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN and DSEN bits at the time the instruction is exe-
cuted. If another SLEEP instruction is executed, the
device will enter the power-managed mode specified
by IDLEN and DSEN at that time. If IDLEN or DSEN
have changed, the device will enter the new
power-managed mode specified by the new setting.
Timer1 oscillator and/or RTCC may optionally be
enabled
internal low-power RC oscillator
The normal, full-power execution mode; primary
clock source (defined by FOSC<2:0>)
Secondary – Timer1 oscillator
Postscaled internal clock
Primary clock source (defined by FOSC<2:0>)
Secondary – Timer1 oscillator
Postscaled internal clock
MULTIPLE SLEEP COMMANDS
Available Clock and Oscillator Source
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